PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 417

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Code Violation Counter (Read)
CVCL
CVCH
CV(15:0)
Data Sheet
CV15
CV7
7
7
Code Violations
No function if NRZ or CMI code has been enabled.
If the B8ZS code (bit FMR0.RC(1:0) = 11) is selected, the 16-bit
counter is incremented by detecting violations which are not due to
zero substitution. If FMR2.EXZE is set, additionally excessive zero
strings (more than 7 contiguous zeros) are detected and counted.
If simple AMI coding is enabled (FMR0.RC0/1 = 10) all bipolar
violations are counted. If FMR2.EXZE is set, additionally excessive
zero strings (more than 15 contiguous zeros) are detected and
counted. The error counter does not roll over.
During alarm simulation, the counter is incremented continuously with
every second received bit.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCVC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCVC is
automatically reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
417
T1/J1 Registers
FALC56 V1.2
CV0
CV8
0
0
PEB 2256
2002-08-27
(52)
(53)