PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 363

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XDL(3:1)
Clear Channel Register (Read/Write)
Value after reset: 00
CCB1
CCB2
CCB3
CH(24:1)
Data Sheet
CH17
CH1
CH9
7
Transmit FS/DL-Bit Data
The DL-bit register access is enabled by setting bits FMR1.EDL = 1.
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XDL(3:1) is copied into
a shadow register. The contents is subsequently sent out in the data
stream of the next outgoing multiframe if no transparent mode is
enabled. XDL10 is sent out first.
In F4 frame format only XDL10+XDL11 are transmitted. In F24 frame
format XDL10 to 23 are shifted out. In F72 frame format XDL10 to 37
are transmitted.
The transmit multiframe begin interrupt (XMB) requests that these
registers should be serviced. If requests for new information are
ignored, the current contents is repeated.
Channel Selection Bits
0 =
1 =
CH10
CH18
CH2
H
, 00
Normal operation. Bit robbing information and zero code
suppression (ZCS, B7 stuffing) can change contents of the
selected speech/data channel if assigned modes are enabled
by bits FMR5.EIBR and FMR0.XC(1:0).
Clear channel mode. Contents of selected speech/data
channel are not overwritten by internal or external bit robbing
and ZCS information. Transmission of channel assigned
signaling and control of pulse-density is applied by the user.
H
, 00
CH11
CH19
CH3
H
CH12
CH20
CH4
363
CH13
CH21
CH5
CH14
CH22
CH6
CH15
CH23
CH7
T1/J1 Registers
CH16
CH24
FALC56 V1.2
CH8
0
PEB 2256
2002-08-27
(2F)
(30)
(31)