PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 273

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PEB2256H-V12

Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2256H-V12

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
Common Configuration Register 4 (Read/Write)
Value after reset: 00
CCR4
RADD3
RCRC3
XCRC3
ITF3
XMFA3
Data Sheet
7
RADD3 RCRC3 XCRC3
Receive Address Pushed to RFIFO3
If this bit is set, the received HDLC channel 3 address information (1
or 2 bytes, depending on the address mode selected via
MODE3.MDS03) is pushed to RFIFO3. This function is applicable in
non-auto mode and transparent mode 1.
Receive CRC ON/OFF - HDLC Channel 3
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO3
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO3 by the status
information byte (contents of register RSIS3). The received CRC
checksum will additionally be checked for correctness. If non-auto
mode is selected, the limits for “Valid Frame” check are modified.
Transmit CRC ON/OFF - HDLC Channel 3
If this bit is set, the CRC checksum will not be generated internally. It
has to be written as the last two bytes in the transmit FIFO (XFIFO3).
The transmitted frame is closed automatically with a closing flag.
Interframe Time Fill - HDLC Channel 3
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0 =
1
Transmit Multiframe Aligned - HDLC Channel 3
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
H
Continuous logical "1" is output
Continuous flag sequences are output ("01111110" bit patterns)
The contents of the XFIFO3 is transmitted without multiframe
alignment.
The contents of the XFIFO3 is transmitted multiframe aligned.
273
ITF3
XMFA3
RFT13
RFT03
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(8C)

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