PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 360

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Data Sheet
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0
2046
e.g: 2.048 MHz: MP = 0 to 255; 4.096 MHz: MP = 0 to 511,
8.192 MHz: MP = 0 to 1023, 16.384 MHz: MP = 0 to 2047
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0
193
SD
with maximum delay = 193 SC/SD - 1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = system data rate
MP
MP
(SC/SD) -2
MP
193
2045:X = MP + 2
2047:X = MP - 2046)
(SC/SD) - 3:X = MP + 2 + 7
MP
360
maximum delay:X = MP + 2 - 186
SC/SD
T1/J1 Registers
FALC56 V1.2
B
PEB 2256
)
2002-08-27
SC/