PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 231

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XFS
ECM
SSD0
XAIS
Data Sheet
1 =
Transmit Framing Select
Selection of the transmit framing format can be done independently
of the receive framing format.
0 =
1 =
Error Counter Mode
The function of the error counters is determined by this bit.
0 =
1 =
Select System Data Rate 0
FMR1.SSD0 and SIC1.SSD1 define the data rate on the system
highway. Programming is done with SSD1/SSD0 in the following
table.
00 = 2.048 Mbit/s
01 = 4.096 Mbit/s
10 = 8.192 Mbit/s
11 = 16.384 Mbit/s
Transmit AIS Towards Remote End
Sends AIS on ports XL1, XL2, XOID towards the remote end. The
outgoing data stream which can be looped back through the local loop
to the system interface is not affected.
PCM 24 or T1/J1 mode (see RC0.SJR for T1/J1 selection).
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters are reset with the rising
edge of the corresponding bits in the DEC register.
Every second the error counter is latched and then
automatically reset. The latched error counter state should be
read within the next second. Reading the error counter during
updating should be avoided (do not access an error counter
within 1 µs after the one-second interrupt occurs).
Doubleframe format enabled.
CRC4-multiframe format enabled.
231
FALC56 V1.2
E1 Registers
PEB 2256
2002-08-27