PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 67

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

• Slave mode
• Master mode
The following table shows the clock modes with the corresponding synchronization
sources.
Table 13
Mode
Master
Master
Master
Slave
Slave
Slave
Slave
The jitter attenuator meets the jitter transfer requirements of the ITU-T I.431 and G.735
to 739 (refer to
Data Sheet
In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route
clock. In case of LOS the DCO-R switches automatically to Master mode. If bit
CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.
In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no clock
is supplied on pin SYNC. If an external clock on the SYNC input is applied, the DCO-R
synchronizes to this input. The external frequency can be 2.048 MHz (IPC.SSYF = 0)
or 8.0 kHz (IPC.SSYF = 1).
Internal
LOS Active
independent Fixed to
independent 2.048
independent 8.0 kHz
no
no
yes
yes
System Clocking (E1)
Figure
17)
Fixed to
2.048
2.048
SYNC
Input
V
MHz
V
MHz
Fixed to
V
MHz
DD
DD
DD
System Clocks generated by DCO-R
DCO-R centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
Synchronized to SYNC input (external 2.048
MHz, IPC.SSYF = 0)
Synchronized to SYNC input (external 8.0 kHz,
IPC.SSYF = 1, CMR2.DCF = 0)
Synchronized to line RCLK
Synchronized to line RCLK
CMR1.DCS = 0:
DCO-R is centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
CMR1.DCS = 1:
Synchronized on line RCLK
CMR1.DCS = 0:
Synchronized to SYNC input
(external 2.048 MHz)
CMR1.DCS = 1:
Synchronized on line clock RCLK
67
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27