PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 196

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Table 52
Register
MODE
MODE2
MODE3
RAH(2:1)
RAL(2:1)
GCM(6:1)
RTR(4:1)
TTR(4:1)
TSS2
TSS3
T1/J1 Initialization
For a correct start up of the primary access interface a set of parameters specific to the
system and hardware environment must be programmed after RES goes inactive (high).
Both the basic and the operational parameters must be programmed before the
activation procedure of the PCM line starts. Such procedures are specified in ITU-T
recommendations (e.g. fault conditions and consequent actions). Setting optional
parameters primarily makes sense when basic operation via the PCM line is guaranteed.
Table 53
control bits which are to be programmed in one of the above steps. The sequence is
recommended but not mandatory. Accordingly, parameters for the basic and operational
set up, for example, can be programmed simultaneously. The bit FMR1.PMOD must
always be kept high (otherwise E1 mode is selected). J1 mode is selected by additionally
setting RC0.SJR = 1.
Features like channel loop-back, idle channel activation, clear channel activation,
extensions for signaling support, alarm simulation, etc. are activated later. Transmission
of alarms (e.g. AIS, remote alarm) and control of synchronization in connection with
consequent actions to remote end and internal system depend on the activation
procedure selected.
Data Sheet
gives an overview of the most important parameters in terms of signals and
Initial Values after reset and FMR1.PMOD = 1 (T1/J1) (cont’d)
Initiated
Value
00
00
00
FD
FF
all 00
all 00
all 00
00
00
H
H
H
H
H
H
H
, FF
, FF
H
H
H
H
H
Meaning
Signaling controller disabled
Compare register for receive address cleared
Fixed clock mode selected (1.544 MHz on pin MCLK
required).
No time slots selected
196
Operational Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27