PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 234

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Transmit Service Word Pulseframe (Read/Write)
Value after reset: 00
XSW
XSIS
XTM
XRA
XY(4:0)
Data Sheet
XSIS
7
Spare Bit For International Use
First bit of the service word. Only significant in doubleframe format. If
not used, this bit should be fixed to "1". If one of the time slot 0
transparent modes is enabled (bit XSP.TT0, or TSWM.TSIS), bit
XSW.XSIS is ignored.
Transmit Transparent Mode
0 =
1 =
Transmit Remote Alarm
0 =
1 =
Spare Bits For National Use (Y-Bits, S
These bits are inserted in the service word of every other pulseframe
if S
they should be fixed to “1”.
If one of the time slot 0 transparent modes is enabled (bit XSP.TT0 or
TSWM.TSA(8:4)), bits XSW.XY(4:0) are ignored.
XTM
H
a
-bit register access is disabled (FMR1.ENSA = 0). If not used,
Ports SYPX/XMFS define the frame/multiframe begin on the
transmit
synchronized on this externally sourced frame boundary and
generates the FAS-bits according to this framing. Any change
of the transmit time slot assignment subsequently produces a
change of the FAS-bit positions.
Disconnects the control of the transmit system interface from
the transmitter. The transmitter is now in a free running mode
without any possibility to actualize the multiframe position. The
framing (FAS-bits) generated by the transmitter is not
“disturbed” (in case of changing the transmit time slot
assignment) by the transmit system highway unless register
XC1 is written. Useful in loop-timed applications. For proper
operation
SIC1.XBS(1:0) = 10) has to be enabled.
Normal operation.
Sends remote alarm towards remote end by setting bit 3 of the
service word. If time slot 0 transparent mode is enabled by bit
XSP.TT0 or TSWM.TRA bit is set, bit XSW.XRA is ignored.
XRA
system
the
XY0
234
transmit
highway.
XY1
XY2
elastic
The
n
-Bits, S
transmitter
XY3
buffer
a
-Bits)
FALC56 V1.2
XY4
E1 Registers
0
(2
PEB 2256
is
2002-08-27
frames,
usually
(20)