CY7C63413-PVXC Cypress Semiconductor Corp, CY7C63413-PVXC Datasheet - Page 10

• Manufacturer Part Number: CY7C63413-PVXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63413-PVXC

• Cpu Family: enCoRe II
• Device Core: M8C
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: USB
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25/5.5V
• Operating Supply Voltage (min): 4/4.35V
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Document #: 38-08027 Rev. *B
Clocking
The XTAL
troller. The user can connect a low-cost ceramic resonator or
an external oscillator can be connected to these pins to
provide a reference frequency for the internal clock distribution
and clock doubler.
An external 6-MHz clock can be applied to the XTAL
the XTAL
XTAL
tively shorted to ground.
Reset
The USB Controller supports three types of resets. All
registers are restored to their default states during a reset. The
USB Device Addresses are set to 0 and all interrupts are
disabled. In addition, the Program Stack Pointer (PSP) and
Data Stack Pointer (DSP) are set to 0x00. For USB applica-
tions, the firmware should set the DSP below 0xE8 to avoid a
memory conflict with RAM dedicated to USB FIFOs. The
assembly instructions to do this are shown below:
The three reset types are:
The occurrence of a reset is recorded in the Processor Status
and Control Register located at I/O address 0xFF. Bits 4, 5,
and 6 are used to record the occurrence of POR, USB Reset,
and WDR respectively. The firmware can interrogate these bits
to determine the cause of a reset.
The microcontroller begins execution from ROM address
0x0000 after a POR or WDR reset. Although this looks like
interrupt vector 0, there is an important difference. Reset
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Bus Reset (non hardware reset)
Mov A, E8h
Swap A,dsp
OUT
OUT
IN
pin is not permissible as the internal clock is effec-
and XTAL
pin is left open. Please note that grounding the
; Move 0xE8 hex into Accumulator
; Swap accumulator value into dsp register
since last write to WDT
At least 8.192 ms
Clock Distribution
OUT
(to Microcontroller)
(to USB SIE)
are the clock pins to the microcon-
clk1x
clk2x
8.192 ms
to 14.336 ms
Figure 2. Clock Oscillator On-chip Circuit
Figure 3. Watch Dog Reset (WDR)
Doubler
Clock
WDR goes high
for 2.048 ms
2.048 ms
IN
pin if
30 pF
processing does NOT push the program counter, carry flag,
and zero flag onto program stack. That means the reset
handler in firmware should initialize the hardware and begin
executing the “main” loop of code. Attempting to execute either
a RET or RETI in the reset handler will cause unpredictable
execution results.
Power-On Reset (POR)
Power-On Reset (POR) occurs every time the V
the device ramps from 0V to an internally defined trip voltage
(Vrst) of approximately 1/2 full supply voltage. In addition to the
normal reset initialization noted under “Reset,” bit 4 (PORS) of
the Processor Status and Control Register is set to “1” to
indicate to the firmware that a Power-On Reset occurred. The
POR event forces the GPIO ports into input mode (high
impedance), and the state of Port 3 bit 7 is used to control how
the part will respond after the POR releases.
If Port 3 bit 7 is HIGH (pulled to V
the idle state (DM HIGH and DP LOW) the part will go into a
semi-permanent power down/suspend mode, waiting for the
USB IO to go to one of Bus Reset, K (resume) or SE0. If Port
3 bit 7 is still HIGH when the part comes out of suspend, then
a 128-µs timer starts, delaying CPU operation until the ceramic
resonator has stabilized.
If Port 3 bit 7 was LOW (pulled to V
ms timer, delaying CPU operation until V
then continuing to run as reset.
Firmware should clear the POR Status (PORS) bit in register
0xFF before going into suspend as this status bit selects the
128-µs or 96-ms start-up timer value as follows: IF Port 3 bit 7
is HIGH then 128-µs is always used; ELSE if PORS is HIGH
then 96-ms is used; ELSE 128-µs is used.
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most
Significant Bit (MSB) of the 2-bit Watch Dog Timer Register
transitions from LOW to HIGH. In addition to the normal reset
30 pF
Execution begins at
Reset Vector 0X00
XTALOUT
XTALIN
CC
SS
) and the USB IO are at
) the part will start a 96-
CY7C63413C
CY7C63513C
CY7C63613C
CC
has stabilized,
Page 10 of 32
CC
voltage to
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