CY7C63413-PVXC Cypress Semiconductor Corp, CY7C63413-PVXC Datasheet - Page 2

• Manufacturer Part Number: CY7C63413-PVXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63413-PVXC

• Cpu Family: enCoRe II
• Device Core: M8C
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: USB
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25/5.5V
• Operating Supply Voltage (min): 4/4.35V
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Document #: 38-08027 Rev. *B
The sink current for each DAC I/O pin can be individually
programmed to one of sixteen values using dedicated Isink
registers. DAC bits [1:0] can be used as high current outputs
with a programmable sink current range of 3.2 to 16 mA
(typical). DAC bits [7:2] have a programmable current sink
range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can
be connected together to drive a single output that requires
more sink current capacity. Each I/O pin can be used to
generate a DAC interrupt to the microcontroller and the
interrupt polarity for each DAC I/O pin is individually program-
mable. The DAC port interrupts share a separate “DAC”
interrupt vector.
The Cypress microcontrollers use an external 6-MHz ceramic
resonator to provide a reference to an internal clock generator.
This clock generator reduces the clock-related noise
emissions (EMI). The clock generator provides the 6 and 12-
MHz clocks that remain internal to the microcontroller.
The CY7C63413C/513C/613C are offered with single EPROM
options.
CY7C63613C have 8 Kbytes of EPROM.
These parts include Power-on Reset logic, a Watch Dog Timer,
a vectored interrupt controller, and a 12-bit free-running timer.
The Power-On Reset (POR) logic detects when power is
applied to the device, resets the logic to a known state, and
begins executing instructions at EPROM address 0x0000. The
Watch Dog Timer can be used to ensure the firmware never
gets stalled for more than approximately 8 ms. The firmware
can get stalled for a variety of reasons, including errors in the
code or a hardware failure such as waiting for an interrupt that
never occurs. The firmware should clear the Watch Dog Timer
periodically. If the Watch Dog Timer is not cleared for approx-
imately 8 ms, the microcontroller will generate a hardware
watch dog reset.
The microcontroller supports eight maskable interrupts in the
vectored interrupt controller. Interrupt sources include the USB
Bus-Reset, the 128-µs and 1.024-ms outputs from the free-
running timer, three USB endpoints, the DAC port, and the
The
CY7C63413C,
CY7C63513C
and
the
GPIO ports. The timer bits cause an interrupt (if enabled) when
the bit toggles from LOW “0” to HIGH “1.” The USB endpoints
interrupt after either the USB host or the USB controller sends
a packet to the USB. The DAC ports have an additional level
of masking that allows the user to select which DAC inputs can
cause a DAC interrupt. The GPIO ports also have a level of
masking to select which GPIO inputs can cause a GPIO
interrupt. For additional flexibility, the input transition polarity
that causes an interrupt is programmable for each pin of the
DAC port. Input transition polarity can be programmed for
each GPIO port as part of the port configuration. The interrupt
polarity can be either rising edge (“0” to “1”) or falling edge (“1”
to “0”).
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources as noted above (128-µs and 1.024-ms). The
timer can be used to measure the duration of an event under
firmware control by reading the timer twice: once at the start
of the event, and once after the event is complete. The
difference between the two readings indicates the duration of
the event measured in microseconds. The upper four bits of
the timer are latched into an internal register when the
firmware reads the lower eight bits. A read from the upper four
bits actually reads data from the internal register, instead of the
timer. This feature eliminates the need for firmware to attempt
to compensate if the upper four bits happened to increment
right after the lower 8 bits are read.
The CY7C63413C/513C/613C include an integrated USB
serial interface engine (SIE) that supports the integrated
peripherals. The hardware supports one USB device address
with three endpoints. The SIE allows the USB host to commu-
nicate with the function integrated into the microcontroller.
Finally, the CY7C63413C/513C/613C support PS/2 operation.
With appropriate firmware the D+ and D– USB pins can also
be used as PS/2 clock and data signals. Products utilizing
these devices can be used for USB and/or PS/2 operation with
appropriate firmware.
CY7C63413C
CY7C63513C
CY7C63613C
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