UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 134

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(2) Oscillation stabilization time select register (OSTS)
132
Address: FFFAH
Symbol
OSTS
This register is used to select the oscillation stabilization time from when reset is effected or STOP mode is
released to when oscillation is stabilized.
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. Thus, when releasing the STOP mode by RESET input, the time required to
release is 2
Note Expanded-specification products of PD780078 Subseries only.
Caution
Remark f
X
17
The wait time when STOP mode is released does not include the time (“a” in the figure below)
from when STOP mode is released until the clock starts oscillation.
This also applies when RESET is input and an interrupt request is generated.
Figure 7-3. Format of Oscillation Stabilization Time Select Register (OSTS)
: Main system clock oscillation frequency
OSTS2
Other than above
/fx.
7
0
0
0
0
0
1
After reset: 04H
OSTS1
6
0
0
0
1
1
0
Voltage waveform
of X1 pin
CHAPTER 7 CLOCK GENERATOR
OSTS0
R/W
5
0
0
1
0
1
0
User’s Manual U14260EJ4V0UD
STOP mode is released
Setting prohibited
2
2
2
2
2
12
14
15
16
17
/f
/f
/f
/f
/f
4
0
X
X
X
X
X
a
Selection of oscillation stabilization time
3
0
f
488 s
1.95 ms
3.91 ms
7.82 ms
15.6 ms
X
= 8.38 MHz
OSTS2
2
OSTS1
1
f
341 s
1.36 ms
2.73 ms
5.46 ms
10.9 ms
X
= 12 MHz
OSTS0
Note
0