UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 459

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

16-bit
data
transfer
8-bit
operation
Instruction
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access is executed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
MOVW
XCHW
ADD
ADDC
Mnemonic
2. The number of clocks applies when there is a program in the internal ROM.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
Note 4
Note 4
CHAPTER 24 INSTRUCTION SET
User’s Manual U14260EJ4V0UD
Bytes
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
–
6
6
–
–
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
12 + 2m (addr16)
12 + 2n AX
Note 2
9 + n
5 + n
9 + n
9 + n
9 + n
9 + n
5 + n
9 + n
9 + n
9 + n
10
10
–
8
8
8
8
–
–
–
–
8
–
–
5
–
8
–
–
5
rp
(saddrp)
sfrp
AX
(saddrp)
AX
sfrp
AX
rp
AX
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
word
AX
(saddrp)
sfrp
rp
(addr16)
rp
word
AX
CPU
r + A
r + A + CY
A + byte
A + r
A + (saddr)
A + (addr16)
A + (HL)
A + (HL + byte)
A + (HL + B)
A + (HL + C)
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + CY
A + (HL) + CY
A + (HL + byte) + CY
A + (HL + B) + CY
A + (HL + C) + CY
) selected by the processor clock control
word
AX
AX
(saddr) + byte
(saddr) + byte + CY
Operation
Z AC CY
Flag
457