UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 365

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

Lead Free Status / Rohs Status
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Transmit EEPROM higher address.
Transmit EEPROM lower address.
IIC0
IIC0
Transfer slave address.
IIC0
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Clear INTIIC0.
Clear INTIIC0.
EEPROM higher address
INTIIC0 = 1?
INTIIC0 = 1?
ACKD0 = 1?
ACKD0 = 1?
EEPROM lower address
STD0 = 1?
address, R/W (0)
A
B
Yes
Yes
Yes
Yes
Yes
Figure 18-21. Master Operation Flowchart (2/5)
End (no acknowledgment)
No
No
No
No
No
End (no slave)
User’s Manual U14260EJ4V0UD
Wait until the start condition is detected and
the bus is ready.
Specify writing and transfer the address of
the slave (EEPROM).
Wait until transfer is completed.
Clear INTIIC0 to poll INTIIC0 without using
an interrupt.
If ACK is not sent, it means that the
specified slave does not exist. End
processing.
If a slave does exist, divide the address of
EEPROM (2 bytes) into two, and start
transmitting the address from the higher
byte.
Each time transmission is completed, check
ACK.
Transmit the lower address.
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