UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 333

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UPD78F0078GK-9ET-A

Manufacturer Part Number
UPD78F0078GK-9ET-A
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0078GK-9ET-A

Lead Free Status / Rohs Status
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(5) SO1 output
Caution If a value is written to the TRMD1, DAP1, and DIR1 bits, the output value of the SO1 bit changes.
The status of the SO1 output is as follows if bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is cleared
to 0.
Notes 1. The PM21, P21, and SSE1 bits and the SS1 pin must also be set to actually produce an output from
TRMD1 = 0
TRMD1 = 1
TRMD1
2. Status after reset
the SO1/P21 pin.
Note 2
DAP1 = 0
DAP1 = 1
DAP1
CHAPTER 17 SERIAL INTERFACE CSI1
Table 17-3. SO1 Output Status
User’s Manual U14260EJ4V0UD
DIR1 = 0
DIR1 = 1
DIR1
Low-level output
SO1 latch value (low-level output)
Bit 7 value of SOTB1
Bit 0 value of SOTB1
SO1 Output
Note 2
Note 1
331

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