UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 346

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

344
Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
Condition for clearing (COI0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (TRC0 = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1
• When ALD0 changes from 0 to 1 (arbitration loss)
• When RESET is input
<Master>
• When “1” is output to the first byte’s LSB
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB
<When not used for communication>
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
TRC0
(transfer direction specification bit)
(transfer direction specification bit)
COI0
0
1
0
1
IICE0:
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set to high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Bit 7 of IIC control register 0 (IICC0)
Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3)
Note
(wait cancel)
User’s Manual U14260EJ4V0UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
• When the received address matches the local
Condition for setting (TRC0 = 1)
Master
• When a start condition is generated
• When “0” is output to the first byte’s LSB
Slave
• When “1” is input to the first byte’s LSB
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
(transfer direction specification bit)
(transfer direction specification bit)