UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 287

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 15-4. Maximum Permissible Baud Rate Error and Minimum Permissible Baud Rate Error
Similarly, the maximum permissible data frame length is as follows.
Therefore, the minimum receivable baud rate of the transmission destination is as follows.
Remark Brate: Baud rate of UART2
From the above expressions for the maximum and minimum baud rates, the permissible error of the baud
rate between UART2 and the transmission destination can be calculated as follows.
Caution
Remark k: Value set by MDL27 to MDL20 (8
The accuracy of reception is dependent upon the number of bits in one frame, input clock frequency, and
division ratio k (the higher the input clock frequency and the higher the division ratio k, the higher the
accuracy).
100
255
20
50
8
k
10
11
Maximum Permissible Baud Rate Error (%)
FLmax = 11
FLmax =
BRmin = (FLmax/11)
k:
FL:
The above error tolerance value is the value calculated based on the ideal sample point.
In the actual design, allow margins that include errors of timing for detecting a start
bit.
Value set by MDL27 to MDL20 (8
1 bit data length
=
21k – 2
21k – 2
CHAPTER 15 SERIAL INTERFACE UART2
20k
2k
+3.53
+4.26
+4.56
+4.66
+4.72
FL –
–1
User’s Manual U14260EJ4V0UD
=
k + 2
FL
FL
2k
21k – 2
20k
11
FL
Brate
k
Minimum Permissible Baud Rate Error (%)
255)
k
255)
–3.61
–4.31
–4.58
–4.67
–4.73
285