UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 595

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3rd
Edition
Addition of expanded-specification products to PD780078Y Subseries
Modification of name of the following special function registers (SFR)
• Ports 0 to 8
Addition of 2.1 Expanded-Specification Products and Conventional Products
Modification of value after reset of port register 1 (P1) in Table 5-3 Special
Function Register List
Modification of Figure 6-14 Block Diagram of P40 to P47
Modification of Figure 6-16 Block Diagram of P50 to P57
Modification of Figure 6-17 Block Diagram of P64, P65, and P67
Modification of Figure 6-18 Block Diagram of P66
Addition of port registers (P0 to P8) to 6.3 Port Function Control Registers
Addition of the following figures
• Figure 8-3 Format of 16-Bit Timer Counter 0n (TM0n)
• Figure 8-4 Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
• Figure 8-5 Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
Addition of register setting method to the following sections
• 8.4.1 Interval timer operation
• 8.4.2 External event counter operation
• 8.4.3 Pulse width measurement operations
• 8.4.4 Square-wave output operation
• 8.4.5 PPG output operation
Addition of settings of prescaler mode register 0n (PRM0n) to the following figures
• Figure 8-15
• Figure 8-19
• Figure 8-23
• Figure 8-26
• Figure 8-28
• Figure 8-30
• Figure 8-32
• Figure 8-34
Modification of the following figures
• Figure 8-17 Timing of Interval Timer Operation
• Figure 8-36 PPG Output Operation Timing
• Figure 8-37 Start Timing of 16-Bit Timer Counter 0n (TM0n)
Addition of the following figures
• Figure 9-3 Format of 8-Bit Timer Counter 5n (TM5n)
• Figure 9-4 Format of 8-Bit Timer Compare Register 5n (CR5n)
Port registers 0 to 8
Control Register Settings for Interval Timer Operation
Control Register Settings in External Event Counter Mode
(with Rising Edge Specified)
Control Register Settings for Pulse Width Measurement with
Free-Running Counter and One Capture Register (When
TI00n and CR01n Are Used)
Control Register Settings for Measurement of Two Pulse
Widths with Free-Running Counter
Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers (with
Rising Edge Specified)
Control Register Settings for Pulse Width Measurement by
Means of Restart (with Rising Edge Specified)
Control Register Settings in Square-Wave Output Mode
Control Register Settings for PPG Output Operation
APPENDIX E REVISION HISTORY
Contents
User’s Manual U14260EJ4V0UD
Throughout
CHAPTER 2 OUTLINE
( PD780078Y
SUBSERIES)
CHAPTER 5 CPU ARCHI-
TECTURE
CHAPTER 6 PORT FUNC-
TIONS
CHAPTER 8 16-BIT TIMER/
EVENT COUNTERS 00, 01
CHAPTER 9 8-BIT TIMER/
EVENT COUNTERS 50, 51
Applied to:
(5/7)
593