UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 275

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Notes 1. To specify a parity bit, stop transmission and reception (TXE2 = 0 and RXE2 = 0) before rewriting
Figure 15-3. Format of Asynchronous Serial Interface Mode Register 2 (ASIM2) (2/2)
2. The parity is not identified with this setting. Therefore, bit 2 (PE2) of asynchronous serial interface
3. To specify a data character length, stop transmission and reception (TXE2 = 0 and RXE2 = 0) before
4. To specify the number of stop bits, stop transmission (TXE2 = 0) before rewriting SL2. Reception
5. To specify an interrupt that occurs in case of an error, stop reception (RXE2 = 0) before rewriting
ISEM2
PS21
PS21 and PS20.
status register 2 (ASIS2) is not set and the error interrupt does not occur.
rewriting CL2.
is always performed on the assumption that the number of stop bits is 1.
ISEM2.
CL2
SL2
Note 4
0
0
1
1
Note 3
0
1
0
1
0
1
Note 1
Note 5
PS20
7 bits
8 bits
1 bit
2 bits
INTSR2 is generated
INTSER2 is generated
0
1
0
1
Note 1
CHAPTER 15 SERIAL INTERFACE UART2
Do not output parity bit.
Output 0 parity.
Output odd parity.
Output even parity.
Specification of number of stop bits for transmission
User’s Manual U14260EJ4V0UD
Transmission
Reception error interrupt signal control
Data character length specification
Parity bit specification
Reception without parity
Identified as odd parity.
Identified as even parity.
Reception as 0 parity
Reception
Note 2
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