UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 342

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

340
Note This flag’s signal is invalid when IICE0 = 0.
WTIM0
ACKE0
This bit’s setting is invalid during an address transfer and is valid after the transfer is completed. When in master
mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that
has received a local address, a wait is inserted at the falling edge of the ninth clock after ACK is issued. When
the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• When RESET is input
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• When RESET is input
0
1
0
1
Note
Note
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Interrupt request is generated at the eighth clock’s falling edge.
Master mode:
Slave mode:
Interrupt request is generated at the ninth clock’s falling edge.
Master mode:
Slave mode:
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However,
ACK is invalid during address transfers and is valid when EXC0 = 1.
Figure 18-5. Format of IIC Control Register 0 (IICC0) (2/4)
After output of eight clocks, clock output is set to low level and wait is set.
After input of eight clocks, the clock is set to low level and wait is set for master device.
After output of nine clocks, clock output is set to low level and wait is set.
After input of nine clocks, the clock is set to low level and wait is set for master device.
User’s Manual U14260EJ4V0UD
Control of wait and interrupt request generation
Acknowledgment control
Condition for setting (WTIM0 = 1)
• Set by instruction
Condition for setting (ACKE0 = 1)
• Set by instruction