UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 185

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.6 Cautions for 16-Bit Timer/Event Counters 00, 01
(1) Timer start errors
(2) 16-bit timer capture/compare register setting
(3) Capture register data retention timing
(4) Valid edge setting
Remark n = 0, 1
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock.
In the clear & start mode entered on a match between TM0n and CR00n, set a value other than 0000H to 16-
bit timer capture/compare register 00n (CR00n). This means a 1-pulse count operation cannot be performed
when 16-bit timer/event counter 0n is used as an external event counter.
The values of 16-bit timer capture/compare registers 00n and 01n (CR00n and CR01n) are not guaranteed after
16-bit timer/event counter 0n has been stopped.
Set the valid edge of the TI00n pin after setting bits 2 and 3 (TMC0n2 and TMC0n3) of 16-bit timer mode control
register 0n (TMC0n) to 0, 0, respectively, and then stopping the timer operation. The valid edge is set by bits
4 and 5 (ES00n and ES01n) of prescaler mode register 0n (PRM0n).
TM0n count value
Count clock
Figure 8-37. Start Timing of 16-Bit Timer Counter 0n (TM0n)
CHAPTER 8 16-BIT TIMER/EVENT COUNTERS 00, 01
Timer start
0000H
User’s Manual U14260EJ4V0UD
0001H
0002H
0003H
0004H
183