ACS8582 Semtech Corporation, ACS8582 Datasheet

ACS8582

Manufacturer Part Number

ACS8582

Description

Manufacturer

Semtech Corporation

Datasheet

1.ACS8582.pdf (114 pages)

Current page: 1 of 114
Download datasheet (3Mb)

Welcome to the datasheet for the Semtech ACS8582

integrated circuit.

The electronic edition of this datasheet contains

hyperlinks that are colored blue. Click on a link to navigate

directly the respective topic.

The ACS8582 is a highly integrated, single-chip solution

for the Synchronous Equipment Timing Source (SETS)

function in a SONET or SDH Network Element. The device

generates SONET or SDH Equipment Clocks (SEC) and

Frame Synchronization clocks. The ACS8582 is fully

compliant with the required international specifications

and standards.

The device supports Free-run, Locked and Holdover

modes, with mode selection controlled either

automatically by an internal state machine or forced by

independent input SEC reference clock sources from

Recovered Line Clock, PDH network, and Node

Synchronization.

The ACS8582 generates independent SEC and BITS

clocks, an 8 kHz Frame Synchronization clock and a 2 kHz

Multi-Frame Synchronization clock, with programmable

pulse width and polarity. The ACS8582 includes a serial

port, which can be SPI compatible, providing access to the

configuration and status registers for device setup.

The ACS8582 supports IEEE 1149.1 JTAG boundary scan.

The User can choose between OCXO or TCXO to define the

Stratum and/or Holdover performance required.

Revision 1.00/March 2008 ©Semtech Corp.

About this Datasheet

ADVANCED COMMUNICATIONS

ADVANCED COMMS & SENSING

Description

CONFIDENTIAL

FINAL

Synchronous Equipment Timing Source for Stratum 3/4E

Page 1

All standards referred to in this datasheet are listed in

References and Associated

Features

References to Standards

Suitable for Stratum 3, 4E and SONET Minimum Clock

(SMC) or SONET/SDH Equipment Clock (SEC)

applications (to Telcordia 1244-CORE Stratum 3 and

GR-253, and ITU-T G.813 Options I and II

specifications).

Accepts two individual input reference clocks with

robust input clock source quality monitoring for T0

path.

Independent T4 DPLL with independent input.

Simultaneously generates four output clocks, plus two

Sync pulse outputs.

Absolute Holdover accuracy better than 7.5 x 10

(instantaneous); holdover stability defined by choice

of external XO.

Programmable PLL bandwidth, for wander and jitter

tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps.

Automatic hit-less source switchover on loss of input

Serial SPI compatible interface.

IEEE 1149.1 JTAG Boundary Scan.

Single 3.3 V operation.

Documents.

and SMC Systems

ACS8582

DATASHEET

www.semtech.com

-14

Related parts for ACS8582

Related keywords

ACS8582 datasheet
ACS8582 data sheet
ACS8582 pdf datasheet
ACS8582 component
ACS8582 part
ACS8582 distributor
ACS8582 RoHS
ACS8582 datasheet download