ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 42

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Each register, or register group, is described in the
register map
description tables.
Register Organization
The ACS8582 uses 8-bit registers, each identified by a
register name and corresponding address (0x0). In this
datasheet, the registers are presented in ascending
address order with the architecture shown in
Figure 14 ACS8582 Register Architecture
Some registers carry several individual data fields of
various sizes, from single-bit values (e.g. flags) upwards.
Several data fields are spread across multiple registers,
as shown in the register map. Shaded areas in the map
are "don't care" and writing either 0 or 1 will not affect any
function of the device. Bits labeled "Set to zero" or "Set to
one" must be set as stated during initialization of the
device, either following power- up, or after a power-on
reset (POR). Failure to correctly set these bits may result
in the device operating in an unexpected way.
CAUTION! Do not write to any undefined register
addresses as this may cause the device to operate in a
test mode. If an undefined register has been
inadvertently addressed, the device should be reset to
ensure the undefined registers are at default values.
Multi-word Registers
For multi-word registers (e.g. Reg. 0C & Reg. 0D), all the
words have to be written to their separate addresses
without any other access taking place, before their
combined value takes effect. If this write sequence is
interrupted, the sequence will be ignored. Reading a
multi-word register freezes all the bits in the multi-word
register, so that all the bits correspond to the same
complete word.
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Map
(Table
20) and subsequent register
CONFIDENTIAL
Figure
14.
FINAL
Page 42
Register Access
Most registers are of one of two types; configuration
registers or status registers. The exceptions are the
chip_id register (Reg. 00) and chip_revision registers
(Reg. 02).
Configuration registers can be written to, or read from, at
any time. The complete 8-bit register must be written,
even if only one bit is being modified.
All status registers may be read at any time. In some
status registers (such as the sts_interrupts register
Reg. 05, Reg. 06 & Reg. 08), any individual data field may
be cleared by writing a 1 into each bit of the field. Writing
a 0 value into a bit will not affect the value of the bit.
A description of each register is given in
register description tables.
Configuration Registers
Each configuration register reverts to a default value on
power-up or following a reset. Most default values are
fixed, but some will be pin-settable. All configuration
registers can be read out over the microprocessor port.
Status Registers
The Status Registers contain readable registers. They may
all be read from outside the chip but are not writeable
from outside the chip (except for the clearing operation
described in
are read via shadow registers to avoid data hits due to
dynamic operation. Each individual status register has a
unique location.
Interrupt Enable and Clear
Interrupt requests are flagged onto output pin INTREQ.
The active state (High or Low) of this pin is programmable
and it can either be driven, or set to high impedance,
when it is non-active (Reg. 7D refers). Bits in the interrupt
status register are set (High) by the following conditions;
1. Any reference source becoming valid or going invalid.
2. A change in the operating state (e.g. Locked, Holdover
3. A brief loss of the currently selected reference source.
4. An AMI input error.
All interrupt sources (see Reg. 05, Reg. 06 & Reg. 07) are
maskable via the mask register (see Reg. 43, Reg. 44 &
Reg. 45), each interrupt source being enabled by writing a
1 to the appropriate bit.
etc.)
Register Access
above). All status registers
ACS8582
Table 20
DATASHEET
www.semtech.com
and the