ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 68

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Address (hex):
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
freq_mon_clk
Bit No.
Bit 7
7
6
5
4
3
48
cnfg_monitors
los_flag_on_
TDO
Description
freq_mon_clk
Bit to select the source of the clock to the frequency
monitors to be either from the output clock or
directly from the crystal oscillator.
los_flag_on_TDO
Bit to select whether the main_ref_fail interrupt
from the T0 DPLL is flagged on the TDO pin. If
enabled this will not strictly conform to the IEEE
1149.1 JTAG standard for the function of the TDO
pin. When enabled, the TDO pin will simply mimic
the state of the main_ref_fail interrupt status bit.
ultra_fast_switch
Bit to enable ultra-fast switching mode. When in this
mode, the device will disqualify a locked-to source
as soon as it detects a few missing input cycles.
ext_switch
Bit to enable external switching mode. When in
external switching mode, the device is only allowed
to lock to a pair of sources. If the SRCSW pin is High,
the device will be forced to lock to input SEC1
regardless of the signal present on that input. If the
SRCSW pin is Low, the device will be forced to lock
to input SEC2 regardless of the signal present on
that input.
* The default value of this bit is dependent on the
value of the SRCSW pin at power-up.
PBO_freeze
Bit to control the freezing of Phase Build-out
operation. If Phase Build-out has been enabled and
there have been some source switches, then the
input-output phase relationship of the T0 DPLL is
unknown. If Phase Build-out is no longer required,
then it can be frozen. This will maintain the current
input-output phase relationship, but not allow
further Phase Build-out events to take place. Simply
disabling Phase Build-out could cause a phase shift
in the output, as the T0 DPLL re-locks the phase to
zero degrees.
Bit 6
ultra_fast_
switch
Bit 5
Description
ext_switch
CONFIDENTIAL
Bit 4
FINAL
Page 68
(R/W) Configuration register
controlling several input
monitoring and switching options.
PBO_freeze
Bit Value
Bit 3
0
1
0
1
0
1
0
1
0
1
PBO_en
Value Description
Frequency monitors clocked by output of TO DPLL.
Frequency monitors clocked by crystal oscillator
frequency.
Normal mode, TDO complies with IEEE 1149.1.
TDO pin used to indicate the state of the
main_ref_fail interrupt status. This allows a system
to have a hardware indication of a source failure
very rapidly.
Currently selected source only disqualified by Leaky
Bucket or frequency monitors.
Currently selected source disqualified after less
than 3 missing input cycles.
Normal operation mode.
External source switching mode enabled. Operating
mode of the device is always forced to be “locked”
when in this mode.
Phase Build-out not frozen.
Phase Build-out frozen, no further Phase Build-out
events will occur.
Bit 2
Default Value
freq_monitor_
soft_enable
Bit 1
ACS8582
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0000 0101*
freq_monitor_
hard_enable
Bit 0