ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 64

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Address (hex):
Address (hex):
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:0]
Bit 7
[7:2]
[1:0]
41
42
cnfg_DPLL_freq_limit
[7:0]
Description
DPLL_freq_limit_value[7:0]
This register defines the extent of frequency offset
to which either the T0 or the T4 DPLL will track a
source before limiting- i.e. it represents the pull-in
range of the DPLLs. The offset of the device is
determined by the frequency offset of the DPLL
when compared to the offset of the external crystal
oscillator clocking the device. If the oscillator is
calibrated using cnfg_nominal_frequency Reg. 3C
and Reg. 3D, then this calibration is automatically
taken into account. The DPLL frequency limit limits
the offset of the DPLL when compared to the
calibrated oscillator frequency.
cnfg_DPLL_freq_limit
[9:8]
Description
Not used.
DPLL_freq_limit_value[9:8]
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
CONFIDENTIAL
DPLL_freq_limit_value[7:0]
Bit 4
Bit 4
FINAL
Page 64
(R/W) Bits [7:0] of the DPLL
frequency limit register.
(R/W) Bits [9:8] of the DPLL
frequency limit register.
Bit Value
Bit Value
Bit 3
Bit 3
-
-
-
Value Description
In order to calculate the frequency limit in ppm,
Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need
to be concatenated. This number is a unsigned
integer and must be multiplied by 0.078 to give a
ppm value. The resulting ppm value represents both
the positive and negative limits.
Value Description
-
See Reg. 41 (cnfg_DPLL_freq_limit) for details.
Bit 2
Bit 2
Default Value
Default Value
DPLL_freq_limit_value[9:8]
Bit 1
Bit 1
ACS8582
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0111 0110
0000 0000
Bit 0
Bit 0