ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 47

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Address (hex):
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
phase_alarm
Bit No.
Bit 7
7
6
5
4
3
2
1
0
03
test_register1
disable_180
Description
phase_alarm
Instantaneous result from T0 DPLL
disable_180
Normally the DPLL will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to 2
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
Not used.
Not used.
Test Control
Leave unchanged or set to 0
8k Edge Polarity
When lock 8k mode is selected for the current input
reference source, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
Test Control
Leave unchanged or set to 0
Test Control
Leave unchanged or set to 0
Bit 6
Bit 5
Description
CONFIDENTIAL
Bit 4
FINAL
Page 47
(R/W) Register containing various
test controls (not normally used).
Set to 0
Bit Value
Bit 3
0
1
0
1
0
0
1
0
0
-
-
8k Edge Polarity Set to 0
Value Description
T0 DPLL reporting phase locked.
T0 DPLL reporting phase lost.
T0 DPLL automatically determines frequency lock
enable.
T0 DPLL forced to always frequency and phase lock.
-
-
-
Lock to falling clock edge.
Lock to rising clock edge.
-
-
Bit 2
Default Value
Bit 1
ACS8582
DATASHEET
www.semtech.com
0001 0000
Set to 0
Bit 0