ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 100

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

JTAG
The JTAG connections on the ACS8582 allow a full
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1, with the following minor
exceptions, and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
2. In common with some other manufacturers, pin TRST
The JTAG timing diagram is shown in
Figure 15 JTAG Timing
Table 21 JTAG Timing (see
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Electrical Specifications
Cycle Time
TMS/TDI to TCK rising edge time
TCK rising to TMS/TDI hold time
TCK falling to TDO valid
from the core, and so do not support INTEST. However
this does not affect board testing.
is internally pulled Low to disable JTAG by default. The
standard is to pull High. The polarity of TRST is as the
standard: TRST High to enable JTAG boundary scan
mode, TRST Low for normal operation.
Parameter
TCK
TMS
TDO
TDI
Figure
15)
Figure
t
SUR
Symbol
t
t
t
t
DOD
SUR
CYC
HT
15.
CONFIDENTIAL
t
HT
FINAL
Page 100
Minimum
50
23
3
Over-voltage Protection
The ACS8582 may require Over-Voltage Protection on
input reference clock ports according to ITU
recommendation K.41. Semtech protection devices are
recommended for this purpose (see separate Semtech
data book).
ESD Protection
Suitable precautions should be taken to protect against
electrostatic damage during handling and assembly. This
device incorporates ESD protection structures that
protect the device against ESD damage at ESD input
levels up to at least +/2kV using the Human Body Model
(HBD) MIL-STD-883D Method 3015.7, for all pins.
Latchup Protection
This device is protected against latchup for input current
pulses of magnitude up to at least ±100 mA to JEDEC
Standard No. 78 August 1997.
-
t
CYC
t
DOD
Typical
-
-
-
-
F8110D_022JTAGTiming_01
Maximum
5
-
-
-
ACS8582
DATASHEET
www.semtech.com
Units
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