ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 21

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Table 7 Telcordia GR-1244 CORE Specification
Telcordia specifications are somewhat tighter, requiring a
non-temperature-related drift of less than 40 ppb per day
and a drift of 280 ppb over the temperature range 0 to
+50°C. Please contact Semtech for information on crystal
oscillator suppliers
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
± 50 ppm adjustment would be sufficient to cope with
most crystals, in fact the range is an order of magnitude
larger due to the use of two 8-bit register locations. The
setting of the cnfg_nominal_frequency register allows for
this adjustment. An increase in the register value
increases the output frequencies by 0.0196229 ppm for
each LSB step.
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
range of the register is 0 to 65535 dec, giving an adjustment
range of -771 ppm to +514 ppm of the output frequencies, in
0.0196229 ppm steps.
Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,
then the calibration value in the register to give a - 5 ppm
adjustment in output frequencies to compensate for the
crystal inaccuracy, would be:
39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).
Output Wander
Wander and jitter present on the output clocks are
dependent on:
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Tolerance
Drift
(Frequency Drift
over supply
voltage range of
+2.7 V to +3.3 V)
The magnitudes of wander and jitter on the selected
input reference clock (in Locked mode)
The internal wander and jitter transfer characteristic
(in Locked mode)
The jitter on the local oscillator clock
The wander on the local oscillator clock (in Holdover
mode).
Parameter
±4.6 ppm over 20 year lifetime
±0.05 ppm/15 seconds @ constant temp.
±0.04 ppm/15 seconds @ constant temp.
±0.28 ppm/over temp. range 0 to +50°C
Value
CONFIDENTIAL
FINAL
Page 21
Wander and jitter are treated in different ways to reflect
their differing impacts on network design. Jitter is always
strongly attenuated, whilst wander attenuation can be
varied to suit the application and operating state. Wander
and jitter attenuation is performed using a digital phase
locked loop (DPLL) with a programmable bandwidth. This
gives a transfer characteristic of a low pass filter, with a
programmable pole. It is sometimes necessary to change
the filter dynamics to suit particular circumstances - one
example being when locking to a new source, the filter can
be opened up to reduce locking time and can then be
tightened again to remove wander. A change between
different bandwidths for locking and for acquisition is
handled automatically within the ACS8582.
There may be a phase shift across the ACS8582 between
the selected input reference source and the output clock
over time, mainly caused by frequency wander in the
external oscillator module. Higher stability XOs will give
better performance for MTIE. The oscillator becomes
more critical at DPLL bandwidth near to or below 0.1 Hz
since the rate of change of the DPLL may be slow
compared to the rate of change of the oscillator
frequency. Shielding of the OCXO or TCXO can further slow
down the rate of change of temperature and hence
frequency, thus improving output wander performance.
The phase shift may vary over time but will be constrained
to lie within specified limits. The phase shift is
characterized using two parameters, MTIE (Maximum
Time Interval Error) and TDEV (Time Deviation) which,
although being specified in all relevant specifications,
differ in acceptable limits in each one.
Typical measurements for the ACS8582 are shown in
Figure
typical measurement of phase error accumulation in
Holdover mode operation.
5, for Locked mode operation.
Figure 6
ACS8582
DATASHEET
www.semtech.com
shows a