ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 38

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Table 16 O1 to O4 Output Frequency Selection
Digital Frequencies
It can be seen from
Digital1 and Digital2 can be selected. Digital1 is a single
frequency selected from the range shown in
Digital2 is another single frequency selected from the
same range. The T0 LF output DFS block shown in the
diagram and clocked either by the T0 77M output DFS
block or via the T0 output APLL, generates these two
frequencies. The input clock frequency of the DFS is
always 77.76 MHz and as such has a period of
approximately 12 ns. The jitter generated on the Digital
outputs is relatively high, due to the fact that they do not
pass through an APLL for jitter filtering. The minimum
level of jitter is when the T0 path is in analog feedback
mode, when the pk-pk jitter will be approximately 12 ns
(equivalent to a period of the DFS clock). The maximum
jitter is generated when in digital feedback mode, when
the total is approximately 17 ns.
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Value in Register
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 16
that frequencies listed as
Off
2 kHz
8 kHz
T0 APLL/2
Digital1
T0 APLL/1
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/4
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/8
T4 APLL/4
Output Frequency for given “Value in Register” for each Output Port’s cnfg_output_frequency Register
O1, Reg. 62 Bits [7:4]
Table
CONFIDENTIAL
17.
Off
2 kHz
8 kHz
Digital2
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/4
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/8
T4 APLL/4
O2, Reg. 60 Bits [7:4]
FINAL
Page 38
FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs
Table 16
8 kHz can be selected. The FrSync and MFrSync outputs,
and 2 kHz and 8 kHz available from the O1 to O4 outputs,
are always supplied from the T0 path.
The outputs can be either clocks (50:50 mark-space) or
pulses and can be inverted. When pulses are configured
on the output, the pulse width will be one cycle of the
output of O3 (O3 must be configured to generate at least
1544 kHz to ensure that pulses are generated correctly).
Figure 11
controls in Reg. 7A. There is an identical arrangement
with Reg. 7A bits [1:0] and the 2 kHz/MFrSync outputs.
Outputs FrSync and MFrSync can be disabled via Reg. 63
bits [7:6].
shows that frequencies listed as 2 kHz and
shows the various options with the 8 kHz
2 kHz
8 kHz
Digital2
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/4
T4 APLL/64
T4 APLL/48
T4 APLL/16
T4 APLL/8
T4 APLL/4
Off
O3, Reg. 61 Bits [3:0]
Off
2 kHz
8 kHz
Digital2
Digital1
T0 APLL/48
T0 APLL/16
T0 APLL/12
T0 APLL/8
T0 APLL/6
T0 APLL/4
T4 APLL/2
T4 APLL/48
T4 APLL/16
T4 APLL/8
T4 APLL/4
O4, Reg. 62 Bits [3:0]
ACS8582
DATASHEET
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