ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 93

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Address (hex):
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
coarse_lim_
phaseloss_en
Bit No.
Bit 7
7
6
5
4
74
cnfg_phase_loss_coarse_limit
wide_range_en multi_ph_resp
Description
coarse_lim_phaseloss_en
Register bit to enable the coarse phase detector,
whose range is determined by
phase_loss_coarse_limit Bits [3:0]. This register
sets the limit in the number of input clock cycles (UI)
that the input phase can move by before the DPLL
indicates phase lost.
wide_range_en
To enable the device to be tolerant to large amounts
of applied jitter and still do direct phase locking at
the input frequency rate (up to 77.76 MHz), a wide
range phase detector and phase lock detector is
employed. This bit enables the wide range phase
detector. This allows the device to be tolerant to,
and therefore keep track of, drifts in input phase of
many cycles (UI). The range of the phase detector
is set by the same register used for the phase loss
coarse limit (Bits [3:0]).
multi_ph_resp
Enables the phase result from the coarse phase
detector to be used in the DPLL algorithm. Bit 6
should also be set when this is activated. The
coarse phase detector can measure and keep track
over many thousands of input cycles, thus allowing
excellent jitter and wander tolerance. This bit
enables that phase result to be used in the DPLL
algorithm, so that a large phase measurement gives
a faster pull-in of the DPLL. If this bit is not set then
the phase measurement is limited to ±360º which
can give a slower pull-in rate at higher input
frequencies, but could also be used to give less
overshoot.
Setting this bit in direct locking mode, for example
with a 19.44 MHz input, would give the same
dynamic response as a 19.44 MHz input used with
8 k locking mode, where the input is divided down
internally to 8 kHz first.
Not used.
Bit 6
Bit 5
Description
CONFIDENTIAL
Bit 4
FINAL
Page 93
(R/W) Register to configure some
of the parameters of the T0 DPLL
phase detector.
Bit Value
Bit 3
0
1
0
1
0
1
-
Value Description
Phase loss not triggered by the coarse phase lock
detector.
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_coarse_limit,
Bits [3:0].
Wide range phase detector off.
Wide range phase detector on.
DPLL phase detector limited to ±360º (±1 UI).
However it will still remember its original phase
position over many thousands of UI if Bit 6 is set.
DPLL phase detector also uses the full coarse
phase detector result. It can now measure up to:
±360º x 8191 UI = ±2,948,760º.
-
phase_loss_coarse_limit
Bit 2
Default Value
Bit 1
ACS8582
DATASHEET
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1000 0101
Bit 0