ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 28

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Using the DPLLs for Accurate Frequency and Phase
Reporting
The frequency monitors in the ACS8582 perform
frequency monitoring with a programmable acceptable
limit of up to ±60.96 ppm. The resolution of the
measurement is 3.8 ppm and the measured frequency
can be read back from Reg. 4C, with channel selection at
Reg. 4B. For more accurate measurement of both
frequency and phase, the T0 and T4 DPLLs and their
phase detectors, can be used to monitor both input
frequency and phase. The T0 DPLL is always monitoring
the currently locked to source, but if the T4 path is not
used then the T4 DPLL can be used as a roving phase and
frequency meter. Via software control it could be switched
to monitor each input in turn and both the phase and
frequency can be reported with a very fine resolution.
The registers sts_current_DPLL_frequency (Reg. 0C, 0D
and 07) report the frequency of the T0 or T4 DPLL with
respect to the external crystal XO frequency (after
calibration via Reg. 3C, Reg. 3D if used). The selection of
T4 or T0 DPLL reporting is made via Reg. 4B, Bit 4. The
value is a 19-bit signed number with one LSB
representing 0.0003068 ppm (range of ±80 ppm). This
value is actually the integral path value in the DPLL, and
as such corresponds to an averaged measurement of the
input frequency, with an averaging time inversely
proportional to the DPLL bandwidth setting. Reading this
regularly can show how the currently locked source is
varying in value e.g. due to frequency wander on its input.
The input phase, as seen at the DPLL phase detector, can
be read back from register sts_current_phase, Reg. 77
and 78. T0 or T4 DPLL phase detector reporting is again
controlled by Reg. 4B, Bit 4. One LSB corresponds to
approximately 0.7 degrees phase difference. For the T0
DPLL this will be reporting the phase difference between
the input and the internal feedback clock. The phase
result is internally averaged or filtered with a -3 dB
attenuation point at approximately 100 Hz. For low DPLL
bandwidths, 0.1 Hz for example, this measured phase
information from the T0 DPLL gives input phase wander in
the frequency band from for example 0.1 Hz to 100 Hz.
This could be used to give a crude input MTIE
measurement up to an observation period of
approximately 1000 seconds using external software.
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
CONFIDENTIAL
FINAL
Page 28
Output Clock Ports
The device supports a set of main output clocks, O1 to O4
and a pair of secondary Sync outputs, FrSync and
MFrSync. The four main output clocks are independent of
each other and are individually selectable. The two
secondary output clocks, FrSync and MFrSync, are
derived from the T0 path only. The frequencies of the
main output clocks are selectable from a range of pre-
defined spot frequencies, as defined in
technologies are TTL/CMOS for all outputs except O1
which can be PECL or LVDS.
PECL/LVDS Output Port Selection
The choice of PECL or LVDS compatibility for Output O1 is
programmed via the cnfg_differential_outputs register,
Reg. 3A.
Output Frequency Selection and Configuration
The output frequency of outputs O1 to O4 is controlled by
a number of interdependent parameters. These
parameters control the selections within the various
blocks shown in
The ACS8582 contains two main DPLL/APLL paths, T0
and T4. Whilst they are largely independent, there are a
number of ways in which these two structures can
interact.
the PLL paths in more detail.
T0 DPLL and APLLs
The T0 DPLL always produces 77.76 MHz regardless of
either the reference frequency (frequency at the input pin
of the device) or the locking frequency (frequency at the
input of the DPLL Phase and Frequency Detector (PFD)).
The input reference is either passed directly to the PFD or
via a pre-divider (not shown) to produce the reference
input. The feedback 77.76 MHz is either divided or
synthesized to generate the locking frequency.
Digital Frequency Synthesis (DFS) is a technique for
generating an output frequency using a higher frequency
system clock (204.8 MHz in the case of the 77.76 MHz
synthesis). However, the edges of the output clock are not
ideally placed in time, since all edges of the output clock
will be aligned to the active edge of the system clock. This
will mean that the generated clock will inherently have
jitter on it equivalent to one period of the system clock.
Figure 10
Figure
is an expansion of
10.
Figure 1
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