ACS8582 Semtech Corporation, ACS8582 Datasheet - Page 88

• Manufacturer Part Number: ACS8582
• Manufacturer: Semtech Corporation

Address (hex):
Revision 1.00/March 2008 ©Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Bit No.
Bit 7
[6:4]
[2:0]
7
3
6B
cnfg_T0_DPLL_damping
Description
Not used.
T0_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6D Bit 7,
cnfg_T0_DPLL_PD2_gain.
Not used.
T0_damping
Register to configure the damping factor of the T0
DPLL. The bit values corresponds to different
damping factors, depending on the bandwidth
selected. Damping factor of 5 being the default
(011).
The Gain Peak for the Damping Factors given in the
Value Description (right) are tabulated below.
Damping Factor
Bit 6
10
20
1.2
2.5
5
T0_PD2_gain_alog_8k
Bit 5
Description
Gain Peak
0.4 dB
0.2 dB
0.1 dB
0.06 dB
0.03 dB
CONFIDENTIAL
Bit 4
FINAL
Page 88
(R/W) Register to configure the
damping factor of the T0 DPLL,
along with the gain of the Phase
Detector 2 in some modes.
Bit Value
Bit 3
001
010
011
100
101
000
110
111
-
-
-
Value Description
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
T0 DPLL damping factor at the following bandwidths
frequency selections:
<4 Hz
5
5
5
5
5
Not used.
Not used.
Not used.
Bit 2
2.5
5
5
5
5
8 Hz
Default Value
18 Hz
1.2
2.5
5
5
5
T0_damping
Bit 1
35 Hz
1.2
2.5
5
10
10
ACS8582
DATASHEET
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0001 0011
70 Hz
1.2
2.5
5
10
20
Bit 0