lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet
lh28f008sc
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lh28f008sc Summary of contents
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... LH28F008SC FEATURES • High-Density Symmetrically-Blocked Architecture – Sixteen 64K Erasable Blocks • High-Performance – Read Access Time • Enhanced Automated Suspend Options – Byte Write Suspend to Read – Block Erase Suspend to Byte Write – Block Erase Suspend to Read • Enhanced Data Protection Features – ...
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... Both devices share a compatible pinout, status reg ister, and software command set. These similarities 17 enable a clean upgrade from the 28F008SA LH28F008SC. When upgrading important to note the following differences • Because of new feature support, the two devices 33 NC have different device codes ...
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... REGISTER DATA COMPARATOR Y-GATING 16 64KB BLOCKS Figure 4. LH28F008SC Block Diagram Writing memory data is performed in byte increments typically within 6 µ pend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks ...
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... LH28F008SC PIN DESCRIPTION SYMBOL TYPE ADDRESS INPUTS: Inputs for addresses during read and write operations INPUT 0 19 Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins ...
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... Outline Package, 1.2 mm thick) and 44-pin SOP (Small Outline Package). Pinouts are shown in Figures 1 and 2. PRINCIPLES OF OPERATION The LH28F008SC SmartVoltage FlashFile memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies dur- ...
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... LH28F008SC Data Protection Depending on the application, the system designer may choose to make the V power supply switchable PP (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired The device accommodates either design prac- PPH1/2/3 tice and encourages optimization of the processor- memory interface ...
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... WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array com- mand functions independently of the V » RP can LH28F008SC » and CE » are active. The » » (whichever ...
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... LH28F008SC BUS OPERATIONS » MODE RP Read Output Disable Standby Deep Power Down V IL Read Identifier Codes Write NOTES: 1. Refer to DC Characteristics. When can for control pins and addresses, and V ...
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... Attempts to issue a block erase or byte to set a block lock-bit. RP » must » clear block lock-bits. The clear block lock-bits operation simultaneously clears all HH LH28F008SC SECOND BUS CYCLE NOTE OPER. ADDRESS DATA Read IA ...
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... LH28F008SC Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the com- mand write, read cycles from addresses shown in Fig- ure 5 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Identifier Code Table for code values) ...
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... V level used for byte write) while in byte write sus- PP pend mode. RP » same RP level used for byte write). LH28F008SC » » output will tran- . However, SR.6 will remain '1' to indicate » » ...
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... LH28F008SC Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a mas- ter lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command ...
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... RP is not V HH ration codes after writing the Read identifier Codes com- mand indicates master and block lock-bit status. 5. SR.0 is reserved for future use and should be masked out when polling the status register. LH28F008SC EFFECT BWSS DPS 2 1 » ...
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... LH28F008SC START WRITE 20H BLOCK ADDRESS WRITE D0H BLOCK ADDRESS READ STATUS REGISTER SUSPEND BLOCK NO ERASE LOOP SUSPEND 0 SR.7 = BLOCK ERASE? 1 FULL STATUS CHECK IF DESIRED BLOCK ERASE COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA (see above RANGE SR ERROR 0 DEVICE 1 SR.1 = PROTECT ...
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... SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. LH28F008SC COMMENTS Data = 40H Addr = Location to be written Byte Data = Data to be written ...
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... LH28F008SC START WRITE B0H READ STATUS REGISTER 0 SR SR.6 = ERASE COMPLETED 1 READ or Read Byte Write BYTE WRITE ? Read Byte Array Data Write Loop NO DONE ? YES WRITE D0H BLOCK READ ARRAY DATA ERASE RESUMED Figure 7. Block Erase Suspend/Resume Flowchart 16 BUS COMMAND OPERATION Write ...
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... Status Register Data Addr = X Standby Check SR WSM Ready 0 = WSM Busy Standby Check SR Byte Write Suspended 0 = Byte Write Completed Write Read Data = FFH Array Addr = X Read Read Array locations other than that being written. Write Byte Write Data = D0H Resume Addr = X LH28F008SC COMMENTS 28F008SC-9 17 ...
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... LH28F008SC START WRITE 60H BLOCK/DEVICE ADDRESS WRITE 01H/F1H BLOCK/DEVICE ADDRESS READ STATUS REGISTER 0 SR FULL STATUS CHECK IF DESIRED SET LOCK-BIT COMPLETED FULL STATUS CHECK PROCEDURE READ STATUS REGISTER DATA (see above RANGE PP SR.3 = ERROR 0 DEVICE 1 SR.1 = PROTECT ERROR 0 COMMAND 1 SEQUENCE SR. ERROR 0 1 SET LOCK-BIT SR ...
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... Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR Clear Block Lock-Bit Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If error is detected, clear the Status Register before attemping retry or other error recovery. LH28F008SC COMMENTS COMMENTS Error Detect , Master Lock-Bit is Set IH 28F008SC-11 19 ...
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... LH28F008SC DESIGN CONSIDERATIONS Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accom- modate multiple memory connections. Three-line control provides for: • Lowest possible memory power dissipation • Complete assurance that data bus contention will not occur ...
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... Output shorted for no more than on second. No more than one output shorted at a time MIN. MAX. 0 +70 3.0 3.6 4.75 5.25 4.50 5.50 LH28F008SC CC + 5.0 V which, during transitions, may overshoot to » and RP may overshoot to PP UNIT TEST CONDITION °C Ambient Temperature and ...
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... LH28F008SC Capacitance T = +25° MHz A SYMBOL PARAMETER TYP. C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 1.5 TEST POINTS 0.0 NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins and output timing ends at 1.5 V. ...
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... µ 200 200 µA V LH28F008SC TEST CONDITIONS = V MAX GND MAX GND CC CC OUT MAX » » ±0 MAX » ...
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... LH28F008SC DC CHARACTERISTICS (Continued) SYM. PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL Output High Voltage (TTL) 0.85 V Output High Voltage (CMOS Lockout during PP V PPLK Normal Operations V during Byte Write Block Erase, or Lock- PPH ...
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... LH28F00SC-85 LH28F00SC-90 V ± MIN. MAX. MIN 400 » » without inpact on t LH28F008SC LH28F008SC-150 UNIT NOTE MIN. MAX. 150 ns 150 ns 150 ns 2 600 ...
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... LH28F008SC V IH ADDRESSES ( ( ( ( HIGH-Z DATA (D/ Figure 15. AC Waveforms for Read Operations 26 DEVICE AND ADDRESS STANDBY SELECTION ADDRESSES STABLE t AVAV t AVEL t GLQV t ELQV t GLQX ...
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... AC Characteristics - Write Operations for Notes 1 through LH28F008SC-120 MIN. MAX. 120 100 100 100 0 » » High 0 » » High 0 LH28F008SC LH28F008SC-150 UNIT NOTE MIN. MAX. 150 ns 1 µ 100 ns 2 100 ...
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... D for block erase, byte write, or lock-bit configuration » should be held until determination of block erase (1M × 8) Flash Memory 7 8 LH28F008SC-120 UNIT MIN. MAX. 120 ns 1 µ 100 ns 100 ...
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... AVAV AVWH t WHAX t ELWL t t WHGL WHEH t t WHWL WHQV1 WLWH t DVWH t WHOX HIGH PHWL WHPL t PHHWH t VPWH » Controlled Write Operations LH28F008SC 5 6 VALID D IN SRD t QVPH t QVVL 008SC-16 29 ...
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... MAX. 120 » Going Low 100 100 100 0 » » High 0 » » High 0 8M (1M × 8) Flash Memory LH28F008SC-150 UNIT NOTE MIN. MAX. 150 ns 1 µ 100 ns 2 100 ...
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... WE » waveform. and D for block erase, byte write, or lock-bit configuration » should be held until determination of block erase, byte write, HH LH28F008SC 7 7 LH28F008SC-120 UNIT NOTE MIN . MAX. 120 ns 1 µ 100 ...
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... LH28F008SC V IH ADDRESSES ( ( ( ( DATA (D/ RY/ PPH3 PPLK V ( NOTES power-up and standby Write block erase or byte write set-up. 3. Write block erase confirm or valid address and data. ...
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... A. Reset During Read Array Mode t PLRH t PLPH MIN. » is tied this CC 100 » » » going high until outputs are valid. LH28F008SC 28F008SC- UNIT NOTE MAX. MIN. MAX. 100 µs 2,3 33 ...
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... LH28F008SC BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE V = 3.3 V ± 0 0°C to +70° SYM. PARAMETER TYP WHQV Byte Write Time 1 t EHQV Block Write Time 2 t WHQV Block Erase Time 2 t EHQV 3 t WHQV Set Lock-Bit Time ...
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... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 23 13.40 [0.528] 16.40 [0.646] 13.00 [0.512] 15.60 [0.614] SEE 22 DETAIL 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 3.25 [0.128] 2.5 [0.098] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] LH28F008SC 14.40 [0.567] 2.9 [0.114] 2.5 [0.098] DETAIL 1.275 [0.050] 0.25 [0.010] 0.05 [0.002 0.80 [0.031] 44SOP 35 ...
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... LH28F008SC 42CSP (CSP042-P-0808) INDEX 8.20 [0.323] 7.80 [0.307] 0.10 [0.004] 0.10 [0.004] 1.0 [1.039] 1.0 [1.039] TYP. TYP. MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 36 0.40 [0.016] (See Detail) DETAIL 0.30 [0.012] 0.48 [0.019] 0.42 [0.017] 0.15 [0.006] 8M (1M × 8) Flash Memory TYP. 42CSP ...
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... DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH28F008SC X -85 Device Type Package Speed Example: LH28F008SCT-85 ( Flash Memory, 85 ns, 40-pin TSOP) 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] 85 Access Time (ns) T 40-pin, 1 TSOP (Type I) (TSOP040-P-1020) N 44-pin, 600-mil SOP (SOP044-P-0600 42-pin, ...
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... LH28F008SC LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. WARRANTY SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice ...