lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 12

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
Set Block and Master
Lock-Bit Commands
enabled via a combination of block lock-bits and a mas-
ter lock-bit. The block lock-bits gate program and erase
operations while the master lock-bit gates block-lock bit
modification. With the master lock-bit not set, individual
block lock-bits can be set using the Set Block Lock-Bit
command. The Set Master Lock-Bit command, in con-
junction with RP
the master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit command
and V
Table for a summary of hardware and software write
protection options.
by a two-cycle command sequence. The set block or
master lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set master lock-bit confirm (and any
device address). The WSM then controls the set lock-
bit algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 10). The CPU can detect the completion of
the set lock-bit event by analyzing the RY
put or status register bit SR.7.
register, bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until a new com-
mand is issued.
tion ensures that lock-bits are not accidentally set. An
invalid Set Block or Master Lock-Bit command will
result in status register bits SR.4 and SR.5 being set
to '1'. Also, reliable operations occur only when
V
this high voltage, lock-bit contents are protected against
alteration.
the master lock-bit be cleared or, if the master lock-bit
is set, that RP
lock-bit set and RP
'1' and the operation will fail. Set block lock-bit opera-
tions while V
and should not be attempted. A successful set master
lock-bit operation requires that RP
tempted with RP
and the operation will fail. Set master lock-bit opera-
tions with V
should not be attempted.
12
CC
A flexible block locking and unlocking scheme is
Set block lock-bit and master lock-bit are executed
When the set lock-bit operation is complete, status
This two-step sequence of set-up followed by execu-
A successful set block lock-bit operation requires that
= V
HH
CC1/2/3
on the RP
IH
IH
< RP
»
= V
and V
< RP
»
»
= V
= V
HH
»
»
»
< V
= V
pin. See Write Protection Analysis
IH
HH
»
. If it is attempted with the master
PP
< V
HH
, SR.1 and SR.4 will be set to '1'
IH
, sets the master lock-bit. After
= V
, SR.1 and SR.4 will be set to
produce spurious results and
HH
PPH1/2/3
produce spurious results
. In the absence of
»
= V
HH
»
/ BY
. If it is at-
»
pin out-
Clear Block Lock-Bits Command
Clear Block Lock-Bits command. With the master lock-
bit not set, block lock-bits can be cleared using only the
Clear Block Lock-Bits command. If the master lock-bit
is set, clearing block lock-bits requires both the Clear
Block Lock-Bits command and V
Write Protection Analysis Table for a summary of hard-
ware and software white protection options.
cycle command sequence. A clear block lock-bits setup
is first written. After the command is written, the device
automatically outputs status register data when read
(see Figure 11). The CPU can detect completion of the
clear block lock-bits event by analyzing the RY
output or status register bit SR.7.
SR.5 should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until another
command is issued.
tion ensures that block lock-bits are not accidentally
cleared. An invalid Clear Block Lock-Bits command
sequence will result in status register bits SR.4 and SR.5
being set to “1”. Also, a reliable clear block lock bits
operation can only occur when V
V
attempted while V
to '1'. In the absence of this high voltage, the block lock-
bits content are protected against alteration. A success-
ful clear block lock-bits operation requires that the master
lock-bit is not set or, if the master lock-bit is set, that
RP
and RP
operation will fail. A clear block lock-bits operation with
V
not be attempted.
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
value. Once the master lock-bit is set, it cannont be
cleared.
PP
IH
PP
All set block lock-bits are cleared in parallel via the
Clear block lock-bits operation is executed by a two-
When the operation is complete, status register bit
This two-step sequence of set-up followed by execu-
If a clear block lock-bits operation is aborted due to
»
< RP
= V
= V
or V
HH
»
PPH1/2/3
= V
»
CC
. If it is attempted with the master lock-bit set
< V
IH
transitioning out of valid range or RP
, SR.1 and SR.5 will be set to '1' and the
HH
. If a clear block lock-bits operation is
produce spurious results and should
PP
V
PPLK
8M (1M × 8) Flash Memory
, SR.3 and SR.5 will be set
HH
on the RP
CC
= V
CC1/2/3
»
pin. See
»
/ BY
»
and
Pin
»