lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 18

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
18
BLOCK/DEVICE ADDRESS
BLOCK/DEVICE ADDRESS
READ STATUS REGISTER
FULL STATUS CHECK PROCEDURE
CHECK IF DESIRED
REGISTER DATA
WRITE 01H/F1H
READ STATUS
SET LOCK-BIT
SET LOCK-BIT
FULL STATUS
SUCCESSFUL
COMPLETED
WRITE 60H
(see above)
SR.4, 5 =
START
SR.7 =
SR.3 =
SR.1 =
SR.4 =
0
0
0
0
1
1
1
1
1
0
SET LOCK-BIT
SEQUENCE
V
COMMAND
PROTECT
PP
Figure 10. Set Block and Master Lock-Bit Flowchart
DEVICE
ERROR
ERROR
ERROR
ERROR
RANGE
OPERATION
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device
in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set
before full status is checked.
If error is detected clear the Status Register before attempting
retry or other error recovery.
OPERATION
Standby
Read
Write
Standby
Standby
Standby
Standby
BUS
Write
BUS
Lock-Bit Confirm
Block or Master
Lock-Bit Setup
Block/Master
COMMAND
COMMAND
Set
Set
Check SR.3
1 = V
Check SR.1
1 = Device Protect Detect
RP = V
(Set Master Lock-Bit Operation)
RP = V
(Set Block Lock-Bit Operation)
Check SR.4, 5
Both 1 = Command
Sequence Error
Check SR.4
1 = Set Lock-Bit Error
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
PP
8M (1M × 8) Flash Memory
IH
IH
Error Detect
, Master Lock-Bit is Set
COMMENTS
COMMENTS
28F008SC-10