lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 10

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
Read Identifier Codes Command
the Read Identifier Codes command. Following the com-
mand write, read cycles from addresses shown in Fig-
ure 5 retrieve the manufacturer, device, block lock
configuration and master lock configuration codes (see
Identifier Code Table for code values). To terminate the
operation, write another valid command. Like the Read
Array command, the Read Identifier Codes command
functions independently of the V
or V
the following information can be read:
Identifier Codes
NOTE:
1. X selects the specific block lock configuration code to be read.
Read Status Register Command
a block erase, byte write, or lock-bit configuration is com-
plete and whether the operation completed success-
fully. It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the
status register until another valid command is written.
The status register contents are latched on the falling
edge of OE
toggle to V
register latch. The Read Status Register command func-
tions independently of the V
or V
10
Manufacturer Code
Device Code
Block Lock Configurations
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
Master Lock Configuration
• Device is Unlocked
• Device is Locked
• Reserved for Future Use
The identifier code operation is initiated by writing
See Figure 5 for the device identifier code memory map.
The status register may be read to determine when
HH
HH
. Following the Read Identifier Codes command,
.
CODE
IH
»
or CE
before further reads to update the status
»
, whichever occurs. OE
PP
ADDRESS
X0002
00000
00001
00003
voltage. RP
PP
and RP
1
»
DQ
DQ
»
or CE
»
DQ
DQ
DQ
DQ
can be V
can be V
DATA
1
1
A6
89
0
0
0
0
- DQ
- DQ
= 0
= 1
= 0
= 1
»
must
7
7
IH
IH
Clear Status Register Command
set to '1' by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Status Register). By allowing sys-
tem software to reset these bits, several operations
(such as cumulatively erasing or locking multiple blocks
or writing several bytes in sequence) may be performed.
The status register may be polled to determine if an
error occurred during the sequence.
ter command (50H) is written. It functions independently
of the applied V
command is not functional during block erase or byte
write suspend modes.
Block Erase Command
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This com-
mand sequence requires appropriate sequencing and
an address within the block to be erased (erase changes
all block data to FFH). Block preconditioning, erase, and
verify are handled internally by the WSM (invisible to
the system). After the two-cycle block erase sequence
is written, the device automatically outputs status reg-
ister data when read (see Figure 6). The CPU can
detect block erase completion by analyzing the output
data of the RY
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new com-
mand is issued.
by execution ensures that block contents are not acci-
dentally erased. An invalid Block Erase command
sequence will result in both status register bits
SR.4 and SR.5 being set to '1'. Also, reliable block era-
sure can only occur when V
V
block contents are protected against erasure. If block
erase is attempted while V
will be set to '1'. Successful block erase requires that
the corresponding block lock-bit be cleared or, if set,
that RP
corresponding block lock-bit is set and RP
and SR.5 will be set to '1'. Block erase operations with
V
not be attempted.
PP
IH
Status register bits SR.5, SR.4, SR.3 and SR.1 are
To clear the status register, the Clear Status Regis-
Erase is executed one block at a time and initiated
When the block erase is complete, status register bit
This two-step command sequence of set-up followed
< RP
= V
»
PPH1/2/3
= V
»
< V
HH
HH
»
/ BY
. If block erase is attempted when the
PP
. In the absence of this high voltage,
produce spurious results and should
»
Voltage. RP
or status register bit SR.7.
8M (1M × 8) Flash Memory
PP
»
can be V
V
PPLK
CC
= V
, SR.3 and SR.5
IH
CC1/2/3
»
or V
= V
IH
HH
, SR.1
. This
and