lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 4

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
PIN DESCRIPTION
4
DQ
SYMBOL
A
RY
0
GND
0
V
V
WE
CE
RP
OE
NC
- A
- DQ
PP
CC
»
/ BY
»
»
»
19
»
7
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
TYPE
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and
sense amplifiers. CE
standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP
operation to locked memeory blocks. Block erase, byte write, or lock-bit configuration
with V
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE Pulse.
READY/BUSY: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY
suspended, and byte write is inactive, byte write is suspended, or the device is in
deep power-down mode. RY
is deselected or data outputs are disabled.
BLOCK ERASE/BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, writing bytes, or configuring lock-bits. With V
memory contents cannot be altered. Block erase, byte write, and lock-bit configura-
tion with an invalid V
should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 3.3 V or 5 V
operation. To switch from one voltage to another, ramp V
ramp V
attempts to the flash memory are inhibited. Device operations at invalid V
(see DC Characteristics) produce spurious results and should not be attempted.
GROUND: Do not float any pins
NO CONNECT: Lead is not internal connected; it may be driven or floated.
»
/ BY
IH
»
CC
»
high indicates that the WSM is ready for new commands, block erase is
= V
< RP
to the new voltage. Do not float any power pins. With V
HH
»
< V
overrides block lock-bits thereby enabling block erase and byte write
HH
PP
»
high deselects the device and reduces power consumption to
produce spurious results and should not be attempted.
»
(see DC Characteristics) produce spurious results and
high enables normal operation. When driven low, RP
»
/ BY
NAME AND FUNCTION
»
is always active and does not float when the chip
»
at V
8M (1M × 8) Flash Memory
CC
HH
down to GND and then
enables setting of the
CC
PP
V
LKO
CC
V
, all write
LKO
voltage
»
inhibits
,