lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 11

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

8M (1M × 8) Flash Memory
Byte Write Command
sequence. Byte write setup (standard 40H or alternate
10H) is written, followed by a second write that speci-
fies the address and data (latched on the rising edge of
WE
and write verify algorithms internally. After the byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU
can detect the completion of the byte write event by
analyzing the RY
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for '1's that do not success-
fully write to '0's. The CUI remains in read status regis-
ter mode until it receives another command.
V
this high voltage, memory contents are protected against
byte writes. If byte write is attempted while V
status register bits SR.4 and SR.5 will be set to '1'. Suc-
cessful byte write requires that the corresponding block
lock-bit be cleared or, if set, that RP
is attempted when the corresponding block lock-bit is
set and RP
write operations with V
results and should not be attempted.
Block Erase Suspend Command
erase interruption to read or byte-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device out-
puts status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to '1').
RY
defines the block erase suspend latency.
to read data from blocks other than that which is sus-
pended. A Byte Write command sequence can also be
issued during erase suspend to program data in other
blocks. Using the Byte Write Suspend command (see
CC
Byte write is executed by a two-cycle command
When byte write is complete, status register bit SR.4
Reliable byte writes can only occur when
The Block Erase Suspend command allows block-
At this point, a Read Array command can be written
»
/ BY
»
) . The WSM then takes over, controlling the byte write
= V
»
will also transition to V
CC1/2/3
»
= V
IH
and V
, SR.1 and SR.4 will be set to '1'. Byte
»
/ BY
»
PP
pin or status register bit SR.7.
IH
= V
< RP
PPH1/2/3
OH
»
< V
. Specification t
HH
»
. In the absence of
= V
produce spurious
HH
. If byte write
PP
V
WHRH2
PPLK
,
Byte Write Suspend Command Section), a byte write
operation can also be suspended. During a byte write
operation with block erase suspended, status register
bit SR.7 will return to '0' and the RY
sition to V
block erase suspend status.
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is writ-
ten to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY
the Erase Resume command is written, the device au-
tomatically outputs status register data when read (see
Figure 8). V
level used for block erase) while block erase is sus-
pended. RP
RP
sume until byte write operations initiated during block
erase suspend have completed.
Byte Write Suspend Command
interruption to read data in other flash memory loca-
tions. Once the byte write process starts, writing the
Byte Write Suspend command resquests that the WSM
suspend the byte write sequence at a predetermined
point in the algorithm. The device continues to output
status register data when read after the Byte Write Sus-
pend command is written. Polling status register bits
SR.7 and SR.2 can determine when the byte write
operation has been suspended (both will be set to '1').
RY
defines the byte write suspend latency.
to read data from locations other than that which is sus-
pended. The only other valid commands while byte write
is suspended are Read Status Register and Byte Write
Resume. After Byte Write Resume command is written
to the flash memory, the WSM will continue the byte
write process. Status register bits SR.2 and SR.7 will
automatically clear and RY
the Byte Write Resume command is written, the device
automatically outputs status register data when read
(see Figure 9). V
V
pend mode. RP
same RP
PP
The only other valid commands while block erase is
The Byte Write Suspend command allows byte write
At this point, a Read Array command can be written
»
»
/ BY
level used for block erase). Block erase cannot re-
level used for byte write) while in byte write sus-
»
will also transition to V
»
OL
level used for byte write).
PP
»
. However, SR.6 will remain '1' to indicate
must also remain at V
must remain at V
»
PP
must also remain at V
must remain at V
»
»
/ BY
/ BY
OH
»
»
PPH1/2/3
will return to V
will return to V
. Specification t
»
IH
/ BY
PPH1/2/3
or V
»
output will tran-
(the same V
IH
LH28F008SC
HH
or V
(the same
(the same
OL
OL
HH
WHRH1
. After
. After
(the
PP
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