lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 9

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

8M (1M × 8) Flash Memory
Command Definitions
NOTES:
1. Bus operations are defined in Bus Definition Table.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Status Register for a description of the status register bits.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes.
5. If the block is locked, RP
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP
8. If the master lock-bit is set, RP
9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Byte Write
Block Erase and Byte
Write Suspend
Block Erase and Byte
Write Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock Bits
IA = Idendifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched on the rising edge of WE
ID = Data read from identifier codes.
See Read Identifier Code Command Section for read identifier code data.
write to locked block while RP
lock-bit is not set, a block lock-bit can be set while RP
block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP
COMMAND
»
must be at V
CYCLES
REQ'D
BUS
»
9
1
1
1
2
1
2
2
2
2
2
is V
»
»
2
must be at V
must be at V
IH
.
HH
OPER.
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
to enable block erase or byte write operations. Attempts to issue a block erase or byte
HH
HH
1
to set a block lock-bit. RP
to clear block lock-bits. The clear block lock-bits operation simultaneously clears all
FIRST BUS CYCLE
ADDRESS
»
is V
WA
BA
BA
X
X
X
X
X
X
X
X
IH
.
2
40H or 10H
DATA
D0H
FFH
B0H
90H
70H
50H
20H
60H
60H
60H
»
must be at V
3
»
or CE
OPER.
Read
Read
Write
Write
Write
Write
Write
HH
»
(whichever goes high first).
SECOND BUS CYCLE
to set the master lock-bit. If the master
1
ADDRESS
WA
BA
BA
IA
X
X
X
»
is V
2
IH
.
DATA
SRD
D0H
D0H
01H
F1H
WD
ID
LH28F008SC
3
NOTE
5, 6
5
4
5
5
7
7
8
9