lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 5

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

8M (1M × 8) Flash Memory
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY
CPU overhead and system power consumption. When
low, RY
erase, byte write, or lock-bit configuration. RY
indicates that the WSM is ready for a new command,
block erase is suspended (and byte write is inactive),
byte write is suspended, or the device is in deep power-
down mode.
cial temperature range (0°C to +70°C) and V
voltage range of 4.75 V - 5.25 V. At lower V
the access times are 90 ns (4.5 V - 5.5 V) and 120 ns
(3.0 V - 3.6 V).
tially reduces active current when the device is in static
mode (addresses not switching). In APS mode, the typi-
cal I
standby mode is enabled. When the RP
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing reset. A reset time (t
switching high until outputs are valid. Likewise, the de-
vice has a wake time (t
to the CUI are recognized. With RP
is reset and the status register is cleared.
Outline Package, 1.2 mm thick) and 44-pin SOP (Small
Outline Package). Pinouts are shown in Figures 1 and 2.
PRINCIPLES OF OPERATION
includes an on-chip WSM to manage block erase, byte
write, and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies dur-
ing block erasure, byte write, and lock-bit configuration,
and minimal processor overhead with RAM-like inter-
face timings.
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and out-
put disable operations.
through the CUI independent of the V
voltage on V
writing, and lock-bit configuration. All functions associ-
ated with altering memory contents–block erase, byte
write, Lock-bit configuration, status, and identifier codes-
are accessed via the CUI and verified through the sta-
tus register.
The RY
The access time is 85 ns (t
The Automatic Power Savings (APS) feature substan-
When CE
The device is available in 40-pin TSOP (Thin Small
The LH28F008SC SmartVoltage FlashFile memory
After initial device power-up or return from deep
Status register and identifier codes can be accessed
CCR
»
/ BY
current is 1 mA at 5 V V
»
/ BY
»
indicates that the WSM is performing a block
PP
»
and RP
»
enables successful block erasure, byte
output gives an additional indicator of
»
pins are at V
PHEL
PHQV
) from RP
AVAV
) is required from RP
CC
»
/ BY
) over the commer-
.
»
CC
at GND, the WSM
»
- high until writes
»
PP
, the I
minimizes both
»
pin is at GND,
voltage. High
CC
CC
CC
»
voltages,
/ BY
CMOS
supply
»
high
»
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase, byte write,
and lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition, inter-
nal verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing the
appropriate command outputs array data, accesses the
identifier codes, or outputs status register data.
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and ex-
ecuted from system RAM during flash memory updates.
After successful completion, reads are again possible
via the Read Array command. Block erase suspend al-
lows sytem software to suspend a block. Byte write sus-
pend allows system software to suspend a byte write to
read data from any other flash memory array location.
Commands are written using standard microproces-
Interface software that initiates and polls progress of
DFFFF
CFFFF
EFFFF
BFFFF
AFFFF
FFFFF
D0000
C0000
9FFFF
8FFFF
7FFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
E0000
B0000
A0000
F0000
90000
80000
70000
60000
50000
40000
30000
20000
10000
00000
Figure 4. Memory Map
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
LH28F008SC
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11
10
9
8
7
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5
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3
2
1
0
28F008SC-4
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