lh28f008sc Sharp Microelectronics of the Americas, lh28f008sc Datasheet - Page 20

• Manufacturer Part Number: lh28f008sc
• Description: 8m 1m ? 8 Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

LH28F008SC
DESIGN CONSIDERATIONS
Three-Line Output Control
arrays. SHARP provides three control inputs to accom-
modate multiple memory connections. Three-line
control provides for:
•
•
decoder should enable CE
to all memory devices and the system’s READ control line.
This assures that only selected memory devices have ac-
tive outputs while deselected memory devices are in
standby mode. RP
POWERGOOD signal to prevent unintended writes dur-
ing system power transitions. POWERGOOD should also
toggle during system reset.
RY
Lock-Bit Configuration Polling
ware method of detecting block erase, byte write and
block-bit configuration completion. It transitions low af-
ter lock erase, byte write, or lock-bit configuration com-
mands and returns to V
executing the internal algorithm.
system CPU or controller. It is active at all times.
RY
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
Power Supply Decoupling
require careful device decoupling. System designers are
interested in three supply current issues; standby cur-
rent levels, active current levels and transient peaks pro-
duced by falling and rising edges of CE
Transient current magnitudes depend on the device out-
puts’ capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its V
and GND and between its V
frequency, low inductance capacitors should be placed
as close as possible to package leads. Additionally, for
every eight devices, a 4.7 µF electrolytic capacitor
should be placed at the array’s power supply connec-
tion between V
come voltage slumps caused by PC board trace
inductance.
20
The device will often be used in large memory
Lowest possible memory power dissipation
Complete assurance that data bus contention will
not occur.
To use these control input efficiently, an address
RY
RY
Flash memory power switching characteristics
»
/ BY
»
/ BY
»
»
/ BY
/ BY
»
is also V
»
and Block Erase, Byte Write, and
»
»
can be connected to an interrupt input of the
is a full CMOS output that provides a hard-
CC
OH
and GND. The bulk capacitor will over-
»
should be connected to the system
when the device is in block erase
OH
»
while OE
when the WSM has finished
PP
and GND. These high-
»
should be connected
»
and OE
CC
»
.
V
system requires that the printed circuit board designer
pay attention to the V
pin supplies the memory cell current for byte writing and
block erasing. Use similar trace widths and layout con-
siderations given to the V
supply traces and decoupling will decrease V
spikes and overshoots.
V
not guaranteed if V
range, V
RP
bit SR.3 is set to '1' along with SR.4 or SR.5,
depending on the attempted operation. If RP
to V
ration, RY
is complete. Then, the opration will abort and the
device will enter deep power-down. The aborted opera-
tion may leave data partially altered. Therefore, the com-
mand sequence must be repeated after normal
operation is restored. Device power-off or RP
to V
ware and is not altered by V
actions. Its state is read array mode upon power-up,
after exit from deep power-down or after V
below V
tion, even after V
must be placed in read array mode via the Read Array
command if subsequent access to the memory array is
desired.
Power-Up/Down Protection
accidental block erasure, byte writing, or lock-bit con-
figuration during power transitions. Upon power-up, the
device is indifferent as to which power supply (V
V
read array mode at power-up.
writes for V
Since both WE
write, driving either to V
two-step command sequence archiecture provides
added level of protection against data alteration.
inadvertent data alteration. The device is disabled while
RP
CC
PP
CC
Updating flash memories that reside in the target
Block erase, byte write and lock-bit configuration are
The CUI latches commands issued by system soft-
After block erase, byte write, or lock-bit configura-
The device is designed to offer protection against
A system designer must guard against spurious
In-system block lock and unlock capability prevents
»
»
IL
IL
) powers-up first. Internal circuitry resets the CUI to
= V
, V
Trace on Printed Circuit Boards
V
during block erase, byte write, or lock-bit configu-
clear the status register.
IH
IL
PP
LKO
CC
or V
regardless of its control inputs state.
»
/ BY
, RP
CC
.
falls outside of a valid V
HH
»
voltages above V
will remain low until the reset operation
»
»
. If V
Transitions
and CE
PP
PP
transitions down to V
PP
PP
falls outside of a valid V
error is detected, status register
IH
»
Power supply trace. The V
must be low for a command
CC
8M (1M × 8) Flash Memory
will inhibit writes. The CUI’s
PP
power bus. Adequate V
or CE
LKO
»
when V
transitions or WSM
CC1/2/3
PPLK
CC
PP
»
»
transiitions
transitions
transitions
PP
range, or
, the CUI
is active.
PPH1/2/3
voltage
PP
PP
PP
or