tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 104
tmp88cs34ng
Manufacturer Part Number
tmp88cs34ng
Description
Cmos 8-bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CS34NG.pdf
(215 pages)
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b.
(2) Transfer mode
a.
SO pin
Shift register
SI pin
Shift register
SCK
SCK
Shift edge
transmit/receive mode.
8-bit transmit mode
1.
2.
The leading edge is used to transmit data, and the trailing edge is used to receive data.
The SIOM (bits 5 and 4 in SBICRA) is used to select a transmit, receive, or
pin
pin
Leading edge
pin input/output).
Trailing edge
input/output).
transmitted data is transferred from the SBIDBR to the shift register and output to the
SO pin in synchronous with the serial clock, starting from the least significant bit
(LSB). When the transmit data is transferred to the shift register, the SBIDBR
becomes empty. The INTSBI (buffer empty) interrupt request is generated to request
new data.
function will be initiated if new data is not loaded to the data buffer register after the
specified 8-bit data is transmitted. When transmit new data is written, automatic-wait
function is canceled.
data is shifted.
When SIOF becomes “0”, the shift register is cleared. So, output of an undefined value
is not prevented at the start of the next transmission.
when an interrupt request is generated and the time when data is written to the
SBIDBR by the interrupt service program.
Data is shifted on the leading edge of the serial clock (at a falling edge of the
Data is shifted on the trailing edge of the serial clock (at a rising edge of the
Set a control register to a transmit mode and write transmit data to the SBIDBR.
After the transmit data is written, set the SIOS to “1” to start data transfer. The
When the internal clock is used, the serial clock will stop and automatic-wait
When the external clock is used, data should be written to the SBIDBR before new
The SO pin is “1” from the time transmission starts until the first data bit is sent.
The transfer speed is determined by the maximum delay time between the time
********
76543210 *7654321 **765432 ***76543
Bit 0
Bit 0
0*******
Figure 2.9.23 Shift Edge
Bit 1
Bit 1
10******
88CS34-104
Bit 2
Bit 2
210*****
(a) Leading edge
(b) Trailing edge
Bit 3
Bit 3
3210**** 43210*** 543210** 6543210* 76543210
****7654
Bit 4
Bit 4
*****765
Bit 5
Bit 5
******76
Bit 6
Bit 6
*******7
Bit 7
Bit 7
TMP88CS34/CP34
*: Don’t care
2007-09-12
SCK
SCK
pin
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