tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 130

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.13.2
(1)
Note 1: The bit positions of a) to e) can be combined.
Note 2: If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order four bits for
Note 1: The bit positions of a) to g) can be combined.
Note 2: If the low order eight bits for the PWM data latch are set to “FFH”, be sure to set the high order six bits for
a)
b)
d)
e)
a)
b)
d)
e)
g)
c)
c)
PWM Output Wave Form
1.
2.
PWM0
f)
PWM0
Bit 13
12-bit Resolution PWM Output
DV1CK = 0) and T
of T
width with a cycle becomes n x t
DV1CK = 1).
pulses. When the upper 4-bit of the PWM data latch is m, the additional pulses are
generated in each of m periods out of 16 periods contained in a T
additional pulses are generated is shown in Table 2.13.1.
14-bit Resolution PWM Output
DV1CK = 0) and T
of T
width with a cycle becomes n x t
DV1CK = 1).
pulses. When the upper 6-bit of the PWM data latch is m, the additional pulses are
generated in each of m periods out of 64 periods contained in a T
additional pulses are generated is shown in Table 2.13.2.
Bit 11
0
0
0
0
0
0
1
Bit position of the lower 4 bits of PWMDRxH
this latch to “00H”.
Bit position of the lower 6 bits of PWMDRxH
this latch to “00H”.
When these are used as 12-bit PWM output, one period is T
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle
The upper 4-bit of the PWM data latch controls a position to output the additional
The relationship between the 4-bit data and the position of T
When these are used as 14-bit PWM output, one period is T
The lower 8-bit of the PWM data latch controls the low level pulse width with a cycle
The upper 6-bit of the PWM data latch controls a position to output the additional
The relationship between the 6-bit data and the position of T
to
0
0
0
0
1
S
S
. The lower 8-bit of the PWM data latch is n (n = 1 to 255), the low level pulse
. The lower 8-bit of the PWM data latch is n (n = 1 to 255), the low level pulse
and
PWM1
Bit 12
0
0
0
0
0
1
0
PWM1
Bit 10
Table 2.13.1 The addition pulse (12 bit mode)
Table 2.13.2 The addition pulse (14 bit mode)
Outputs
0
0
0
1
0
Bit 11
0
0
0
1
0
0
0
output can be selected 12-bit or 14-bit resolution PWM outputs.
M
M
Bit 10
= 2
= 2
0
0
0
1
0
0
0
Bit 9
0
0
1
0
0
14
16
/fc [s] (When DV1CK = 1) and sub-period is T
/fc [s] (When DV1CK = 1) and sub-period is T
Bit 9
88CS34-130
0
0
1
0
0
0
0
Bit 8
0
0
1
0
0
0
0
Bit 8
[s] (t
[s] (t
0
1
0
0
0
0
0
0
0
Relative position of T
pulse is generated. (Number of T
No additional pulse
8
4, 12
2, 6, 10, 14
1, 3, 5, 7, 9, 11, 13, 15
Relative position of T
pulse is generated. (Number of T
No additional pulse
32
16, 48
8, 24, 40, 56
4, 12, 20, 28, 36, 44, 52, 60
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33,
35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63
= 2/fc [s] when DV1CK = 0, t
= 2/fc [s] when DV1CK = 0, t
S
S
in T
in T
M
M
period where the additional
period where the additional
M
M
S (I)
S (I)
M
TMP88CS34/CP34
M
S
S
period.
period.
= 2
= 2
period where the
period where the
is listed)
is listed)
0
S
0
S
13
15
= 4/fc [s] when
= 4/fc [s] when
= T
= T
/fc [s] (When
/fc [s] (When
2007-09-12
M
M
/16.
/64.