tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 58

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Watchdog Timer Register 1
Watchdog Timer Register 2
WDTCR1
WDTCR2
(00034H)
(00035H)
Example: Sets the watchdog timer detection time to 2
Within 3/4 of WDT
detection time
Within 3/4 of WDT
detection time
Note 1: WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”.
Note 2: fc: High-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.
Note 4: The watchdog timer must be disabled or the counter must be cleared immediately before entering to the
Note 5: Just right before disabling the watchdog timer, disable the acceptance of interrupts (DI) and clear the
Note 1: The disable code is invalid unless written when WDTEN = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Clears the binary counter does not clear the source clock.
Note 5: The watchdog timer counter must be disabled by writing the disable code (B1H) to WDRCR2 after writing
WDTOUT
WDTCR2
WDTEN
WDTT
7
7
STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing
the STOP mode.
watchdog timer.
If the watchdog timer is disabled under conditions other than the above, the proper operation cannot be
guaranteed.
It is recommended that the time to clear is set to 3/4 of the detecting time.
WDTCR2 to. “4EH”.
Watchdog timer
enable/disable
Watchdog timer
detection time [s]
Watchdog timer
output select
Watchdog timer control
code write register
6
6
Figure 2.4.2 Watchdog Timer Control Registers
LD
LD
LD
LD
LD
5
5
4
4
(WDTCR2), 4EH
(WDTCR1), 00001101B ;
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
88CS34-58
4EH: Watchdog timer binary counter clear (clear code)
B1H: Watchdog timer disable (disable code)
Others: Invalid
0: Interrupt request
1: Reset output
WDTEN
0: Disable (It is necessary to write the disable code to
1: Enable
3
3
WDTCR2)
00
01
10
11
21
2
2
/fc [s] and resets the CPU malfunction.
WDTT
DV1CK = 0
2
1
2
2
2
;
;
;
;
25
1
23
21
19
/fc
/fc
/fc
/fc
Clears the binary counters
WDTT ← 10, WDTOUT ← 1
Clears the binary counters
(always clear immediately before
Clears the binary counters
Clears the binary counters
and after changing WDTT)
WDTOUT
NORMAL mode
0
0
DV1CK = 1
(Initial value: **** 1001)
(Initial value: **** ****)
TMP88CS34/CP34
2
2
2
2
26
24
22
20
/fc
/fc
/fc
/fc
2007-09-12
Write
only
Write
only