tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 178

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.14.6.7 Display Memory Access
(2) Interrupt generator circuit
(1) Display memory
Note 1: These control registers have a characteristic that immediately when a value is
Note 2: The data written to the display memory takes effect at the same time it is written. When
Note 3: When writing data to or reading data from the display memory, do not use two-byte
Note 4: Allow for at least two instruction cycles between a display memory address write
Note 5: When setting display memory addresses, always be sure to write all of 9 address
counter (DCTR) is counted to the certain value specified by ISDC.
display memory, and one for reading data from the display memory.
Display memory address specification registers
(9 bits)
Display memory data write registers
Display memory bank select register MBK (bit 1 in ORETC)
“0”
“1”
An interrupt request is generated when a falling edge of
Interrupt source select register (1 bit): SVD (bit 4 in ORIRC)
Interrupt generation line specification register (4 bits) ··· ISDC (bit 3 to 0 in ORIRC)
The display memory is accessed for two purposes, one for writing data to the
“0”
“1”
Character code write register (9 bits)
Character ornamentation data write
registers (6 bits)
Character-specific background on/off
specification register (1 bit)
written to the register, the content of the register is transferred as valid data to the
OSD circuit/display memory.
character code or character ornamentation data is written to the display memory while
it is displaying some character, the character may not be displayed correctly. When
writing data to the display memory, make sure no character is being displayed in the
memory location where you are going to write data.
transfer instructions such as “LDW(HL),mn LD rr, (pp).” Otherwise, erroneous data
may be written to the display memory or data may be written to an incorrect
address.
instruction and a data write or read instruction. Also, when continuous writing data
to or reading data from the display memory, allow for at least two instruction cycles
between one write or read instruction and the next. Otherwise, erroneous data may
be written to the display memory or data may be written to an incorrect address.
bits sequentially in order of DMA8 and DMA7 to DMA0.
“0000”
“0001”
“0010”
“1111”
to
···
···
···
···
When writing either character code or character ornamentation data
When writing both character code and character ornamentation data
···
···
···
···
Interrupt request generated when the display line counter (DCTR)
is counted to the certain value which is specified by ISDC.
Interrupt request is generated when a falling edge of
Interrupt request generated when the display line counter is
cleared.
Interrupt request generated at end points of the last scanning
line of the first display line
Interrupt request generated at end points of the last scanning
line of the 2’nd display line
Interrupt request generated at end points of the last scanning
line of the 15’th display line
88CS34-178
··· DMA8 to MDA0 (ORDMA)
··· CRA8 to CRA0 (ORCRA)
··· SLNT, EUL, BLF, RDT,
··· ECBKD (ORDSN register)
GDT, and BDT (ORDSN)
VD
TMP88CS34/CP34
signal or when line
2007-09-12
VD
signal.