tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 23

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Each interrupt vector is independent.
CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled
and disabled by program using the interrupt master enable flag (IMF) and the individual
interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the
interrupt is accepted in the highest priority order as determined by the hardware. Figure 1.5.1
shows the interrupt controller.
(1) Interrupt Latches (IL
(2) Interrupt Enable Register (EIR)
Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources.
The interrupt latch is set to “1” when an interrupt request is generated, and requests the
is set to “1” when an interrupt request is generated, and requests the CPU to accept the
interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt
latches are initialized to “0” during reset.
in the SFR. Except for IL
however, the read-modify-write instruction such as bit manipulation or operation
instructions cannot be used. When interrupt occurred during order execution, the reason is
because interrupt request is cleared. Thus, interrupt requests can be canceled and
initialized by the program. Note that request the interrupt latches cannot be set to “1” by
an instruction. For example, it may be that each latch is cleared even if an interrupt
request is generated during instruction exection.
interrupt request by software is possible.
except for the pseudo non-maskable interrupts (software and watchdog timer interrupts).
Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR;
however, the pseudo non-maskable interrupt cannot be nested more than once at the same
time.
enable flags (EF). These registers are assigned to addresses 0003AH, 0003BH, 0002CH and
0002DH in the SFR, and can be read and written by an instruction (including
read-modify-write instruction such as bit manipulation instructions).
Note: Do not use the read-modify-write instruction for the EIRL (address 0003AH) during
Example 1: Clears interrupt latches
Example 2: Reads interrupt latches
Example 3: Tests an interrupt latch
Interrupt latches are provided for each source, except for a software interrupt. The latch
The interrupt latches are assigned to addresses 0003CH, 0003DH, 0002EH and 0002FH
The contents of interrupt latches can be read out by an instruction. Therefore, testing
The interrupt enable register (EIR) enables and disables the acceptance of interrupts,
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt
DI
LDW
LD
TEST (ILL). 7
JR
pseudo non-maskable interrupt service task. If the read-modify-write instruction is used,
the IMF is not set to “1” after RETN.
(ILL), 1110100000111111B
WA, (ILL)
F, SSET
31
to IL
2
, each latch can be cleared to “0” individually by an instruction;
2
)
88CS34-23
;
;
;
;
Disable interrupt
IL
W ← IL
if IL
12
, IL
7
= 1 then jump
10
H
, A ← IL
to IL
6
← 0
L
TMP88CS34/CP34
2007-09-12