tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 59

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.4.3
2.4.4
(2) Watchdog timer enable
(3) Watchdog timer disable
initialized to “1” during reset, so the watchdog timer operates immediately after reset is
released.
write the clear code (4EH) into WDTCR2. Then, clear WDTEN (bit 3 in WDTCR1) to “0”.
into WDTCR2. If WDTEN is cleared to “0” after the disable code has been written into
WDTCR2, the watchdog timer is not disabled. While it is disabled, its binary counter is
cleared.
Watchdog Timer Interrupt (INTWDT)
contents of the EIR. If a watchdog timer interrupt or a software interrupt is already
accepted, however, the new watchdog timer interrupt waits until the previous interrupt
processing is completed (the end of the [RETN] instruction execution).
interrupt source with WDTOUT.
Watchdog Timer Reset
The reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5 μs at fc = 16.0 MHz).
Note: If there is any fluctuation in the oscillation frequency at the start of clock oscillation, the
Example: Disables watchdog timer
Example:
Example: Watchdog timer interrupt setting up
RESET
The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to “1”. WDTEN is
To disable the watchdog timer, clear the interrupt mask enable flag (IMF) to “0” and
When WDTEN is “0”, the watchdog timer is disabled by writing the disable code (B1H)
This is a pseudo non-maskable interrupt which can be accepted regardless of the
The stack pointer (SP) should be initialized before using the watchdog timer output as an
If the watchdog timer output becomes active, a reset is generated, which drivers the
Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz)
reset time includes error. Thus, regard the reset time as an approximate value.
pin (sink open drain input/output with pull-up) low to reset the internal hardware.
LDW
DI
LD
LDW
EI
LD
LD
WDTT
(WDTCR1), 00001000B
(WDTCR2), 4EH
(WDTCR1), B101H
SP, 023FH
(WDTCR1), 00001000B
00
01
10
11
Watchdog timer detection time [s]
88CS34-59
DV1CK = 0
524.288 m
131.072 m
32.768 m
2.097
NORMAL mode
;
;
;
;
;
;
;
WDTEN ← 1
Disables interrupt acceptance.
Clears the watchdog timer.
Disables the watchdog timer.
Enables interrupt acceptance.
Sets the stack pointer
WDTOUT ← 0
DV1CK = 1
262.1 m
65.5 m
4.194
1.048
TMP88CS34/CP34
2007-09-12