tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 77

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Source clock
Up-counter
Timer register B
INTTC3 interrupt
Source clock
Up-counter
Timer register B
ACAP1
(2) Event counter mode
falling edge can be selected with TC3ES (bit 0 in PMPXCR). The contents of TC3DRA are
compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is
generated and the counter is cleared. Match detect is executed on the falling edge of the
TC3 pin. A match can not be detected, and INTTC3 is not generated when the pulse is still
in a falling state.
required for both the high and low levels of the pulse width.
TC3CR) to “1” (Auto-capture funcion).
instruction) of TC3DRB. Loading the contents of up-counter is not synchronized with
counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is
necessary to consider the count cycle.
Example: Generates an interrupt every 0.5 s, inputting 50 Hz pulses to the TC3 pin.
In this mode, the TC3 pin input pulses are used for counting up Either the rising on
The maximum applied frequency is shown in Table 2.7.2. Two or more machine cycles are
The current contents of up-counter are loaded into TC3DRB by setting ACAP (bit 6 in
The contents of up-counter can be easily confirmed by executing the read instruction (RD
?
Count start
0
?
Table 2.7.2 Source Clock (External Clock) for Timer/Counter
m − 2
LD
LD
LD
n
"H" width
"L" width
1
m − 1
(TC3CR), 00001110B
(TC3DRA), 19H
(TC3CR), 00011100B
Figure 2.7.3 Timer Mode Timing Chart
m − 1
2
3
m
Capture
m
4
Minimum applied frequency [Hz]
88CS34-77
m + 1
NORMAL, IDLE Mode
m + 1
Match detect
m + 2
n − 1 n 0
(a) Timer Mode
(b) Auto-capture
m + 2
2
2
2
2
/fc
/fc
;
;
;
Counter clear
1
Sets TC3 mode and source clock
0.5 s ÷ 1/50 = 25 = 19H
Starts TC3
2
n − 1
n − 1
3
4
n
5
Capture
n
TMP88CS34/CP34
n + 1
6
n + 1
7
2007-09-12