tmp88cs34ng TOSHIBA Semiconductor CORPORATION, tmp88cs34ng Datasheet - Page 187

• Manufacturer Part Number: tmp88cs34ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(8) Functions supporting PAL100/NTSC120
Television System Community) 120 broadcasting systems. Figure 2.14.35 schematically shows
the supported screen scanning method.
display in the next field (1st field).
Note 1: Use software to determine the write timing for PALTRG.
Note 2: It is impossible to normally display the screen on the field of which PALTRG is written.
Note 3: To read the phase detection results PDF0 to PDF2, write “1” to the JEEN jitter elimination
This LSI package supports the PAL (Phase Alternating Lines) 100 and NTSC (National
PAL100 support enable unit: Screen
PAL100 support enable register (1 bit): EPAL100 (bit 5 in the ORDON register)
PAL100 screen display start enable register (1 bit): PALTRG (bit 0 in the ORSTRG register)
To support PAL100/NTSC120, follow this procedure.
Once PALTRG has been written, it becomes possible to support PAL100/NTSC120 for OSD
(a) To use PAL100/NTSC120, set the EPAL100 OSD control register (bit 5 in the ORDON
(b) Read the phase detection results, PDF0 to PDF2, of the horizontal sync signal (HD)
(c) By reading the phase detection results PDF0 to PDF2, the phase of screen scanning is
(d) Write PALTRG (bit 0 in the ORSTRG register) during the second cycle of the 2nd field
Figure 2.14.37 PAL100/NTSC120 Image Scanning Lines (Schematic Diagram)
register) to “1”.
and the vertical sync signal (VD) (bits 6, 5, and 0 in the JESR jitter elimination status
register) each time a VD interrupt occurs.
determined according to the detected field (1st or 2nd field).
(2nd field 2).
control register (bit 2 in the JECR register) to enable the jitter elimination circuit.
1st field 1
A
88CS34-187
1st field 2
A
2nd field 1
A
TMP88CS34/CP34
2nd field 2
A
2007-09-12