AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 105

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.2.4.1
6042E–ATARM–14-Dec-06
Programming
All the commands are protected by the same keyword, which has to be written in the eight
highest bits of the MC_FCR register.
Writing MC_FCR with data that does not contain the correct key and/or with an invalid com-
mand has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR
register. This flag is automatically cleared by a read access to the MC_FSR register.
When the current command writes or erases a page in a locked region, the command has no
effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register.
This flag is automatically cleared by a read access to the MC_FSR register.
In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle
Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see
”MC Flash Mode Register” on page
The programming is done by writing data into the latch buffer and then triggering a program-
ming command that corresponds to the Write Page Command (WP) in the Flash Command
Register MC_FCR. The sequence is as follows:
Figure 20-5. State of the EOP Bit in MC_FSR
When the software reads the Flash Status Register (MC_FSR), the EOP bit is automatically
cleared and the interrupt line is deactivated.
• Write the full page, at any page address, within the internal memory area address space
• If not already done, set the bit EOP (End of Programming) in the Flash Mode Register,
• Write in the field PAGEN of the Flash Command Register (MC_FCR) the Page Number to
• Clear the bit NEBP (No Erase Before Programming) in MC_FMR, if an erase before
• Start the programming by writing the Flash Command Register with the Write Page
• The page defined by PAGEN is first erased if the bit NEBP is set to 0 and then programmed
• When the programming completes, the bit EOP in the Flash Programming Status Register
using only 32-bit access.
depending on whether an interrupt is required or not at the end of programming.
be programmed.
programming is required.
Command.
with the data written in the buffer.
raises. If an interrupt has been enabled by setting the bit EOP in MC_FMR, the interrupt
line of the Memory Controller is activated.
Write the MC_FCR with WP or WPL command
EOP
110).
Programming Time
AT91SAM7A3 Preliminary
Read the MC_FSR
105