AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 505

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.4.3
36.6.5
6042E–ATARM–14-Dec-06
Low-power Mode
Overload
An error active unit takes part in bus communication and sends an active error frame when the
CAN controller detects an error.
An error passive unit cannot send an active error frame. It takes part in bus communication,
but when an error is detected, a passive error frame is sent. Also, after a transmission, an
error passive unit waits before initiating further transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters
are accessible via the CAN_ECR register. The state of the CAN controller is automatically
updated according to these counter values. If the CAN controller is in Error Active state, then
the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the
interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive
Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while
the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit
is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF
bit is set in the CAN_IMR register.
When one of the error counters values exceeds 96, an increased error rate is indicated to the
controller through the WARN bit in CAN_SR register, but the node remains error active. The
corresponding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive over-
load frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in
the CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit
in the CAN_MR register is not set. An overload flag is generated in the same way as an error
flag, but error counters do not increment.
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are
inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP
signal in the CAN_SR register is set. These two fields are exclusive except after a CAN con-
troller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Low-
power Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detec-
tion of 11 consecutive recessive bits on the bus.
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant
bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter
AT91SAM7A3 Preliminary
505